IDT70V28L
High-Speed 3.3V 64K x 16 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Waveform of
BUSY
Arbitration Controlled by
CE
Timing (M/S = V
IH
)
(1,3)
ADDR
"A"
and
"B"
ADDRESSES MATCH
CE
"A"
t
APS
(2)
CE
"B"
t
BAC
BUSY
"B"
4849 drw 13
t
BDC
Waveform of
BUSY
Arbitration Cycle Controlled by Address Match
Timing (M/S = V
IH
)
(1)
ADDR
"A"
t
APS
(2)
ADDR
"B"
MATCHING ADDRESS "N"
t
BAA
BUSY
"B"
4849 drw 14
ADDRESS "N"
t
BDA
NOTES:
1. All timing is the same for left and right ports. Port 鈥淎鈥?may be either the left or right port. Port 鈥淏鈥?is the port opposite from port 鈥淎鈥?
2. If t
APS
is not satisfied, the
BUSY
signal will be asserted on one side or another but there is no guarantee on which side
BUSY
will be asserted.
3. Refer to Truth Table I - Chip Enable.
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range
70V28L15
Com'l Only
Symbol
INTERRUPT TIMING
t
AS
t
WR
t
INS
t
INR
Address Set-up Time
Write Recovery Time
Interrupt Set Time
Interrupt Reset Time
0
0
____
____
70V28L20
Com'l
& Ind
Min.
Max.
Unit
Parameter
Min.
Max.
0
0
____
____
ns
ns
ns
ns
4849 tbl 15
____
____
15
15
20
20
____
____
12