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HIGH-SPEED 3.3V

64K x 16 DUAL-PORT

STATIC RAM

.eatures

True Dual-Ported memory cells which allow simultaneous

access of the same memory location

High-speed access

鈥?Commercial: 15/20ns (max.)

鈥?Industrial: 20ns (max.)

Low-power operation

鈥?IDT70V28L

Active: 440mW (typ.)

Standby: 660碌W (typ.)

Dual chip enables allow for depth expansion without

external logic

IDT70V28 easily expands data bus width to 32 bits or

more using the Master/Slave select when cascading more

than one device

x

x

x

x

IDT70V28L

x

x

x

x

x

x

x

x

x

x

M/S = V

IH

for

BUSY

output flag on Master,

M/S = V

IL

for

BUSY

input on Slave

Busy and Interrupt Flags

On-chip port arbitration logic

Full on-chip hardware support of semaphore signaling

between ports

Fully asynchronous operation from either port

Separate upper-byte and lower-byte controls for multi-

plexed bus and bus matching compatibility

LVTTL-compatible, single 3.3V (鹵0.3V) power supply

Available in a 100-pin TQFP

Industrial temperature range (鈥?0擄C to +85擄C) is available

for selected speeds

.unctional Block Diagram

R/

W

L

UB

L

CE

0L

CE

1L

OE

L

LB

L

R/

W

R

UB

R

CE

0R

CE

1R

OE

R

LB

R

I/O

8-15L

I/O

0-7L

BUSY

L

(1,2)

A

15L

A

0L

64Kx16

MEMORY

ARRAY

70V28

16

16

I/O

8-15R

I/O

Control

I/O

Control

I/O

0-7R

BUSY

R

A

15R

A

0R

(1,2)

Address

Decoder

Address

Decoder

CE

0L

CE

1L

OE

L

R/W

L

SEM

L

ARBITRATION

INTERRUPT

SEMAPHORE

LOGIC

CE

0R

CE

1R

OE

R

R/W

R

SEM

R

(2)

INT

R

4849 drw 01

M/S

NOTES:

1.

BUSY

is an input as a Slave (M/S=V

IL

) and an output when it is a Master (M/S=V

IH

).

2.

BUSY

and

INT

are non-tri-state totem-pole outputs (push-pull).

INT

L

(2)

(1)

JANUARY 2002

DSC-4849/3

1

漏2002 Integrated Device Technology, Inc.

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