最新免费av在线观看,亚洲综合一区成人在线,中文字幕精品无码一区二区三区,中文人妻av高清一区二区,中文字幕乱偷无码av先锋

V103AYLFT Datasheet

  • V103AYLFT

  • TRIPLE 10-BIT LVDS TRANSMITTER FOR VIDEO

  • 11頁

  • ICS

掃碼查看芯片數(shù)據(jù)手冊

上傳產(chǎn)品規(guī)格書

PDF預(yù)覽

V103A
T
RIPLE
10-B
IT
LVDS T
RANSMITTER FOR
V
IDEO
General Description
The V103A LVDS display interface transmitter is
primarily designed to support pixel data transmission
between a video processing engine and a digital video
display. The data rate supports up to SXGA+
resolutions and can be used in Plasma, Rear Projector,
Front Projector, CRT and LCD display applications. It
can also be used in other high-bandwidth parallel data
applications and provides a low EMI interconnect over
a low cost, low bus width cable up to several meters in
length.
The V103A converts 35 bits of CMOS/TTL data,
clocked on the rising or falling edge of an input clock
(selectable), into six LVDS (Low Voltage Differential
Signaling) serial data stream pairs. In video
applications the 35 bits is normally divided into 10 bits
for each R, G and B channel and 5 control bits.
When combined with the V104 LVDS display interface
receiver, the V103A + V104 combination provides a
35-bit wide, 90 MHz transport. The rate of each LVDS
channel is 630 Mbps for a 90MHz data input clock, 945
Mbps for 135MHz.
Features
鈥?/div>
Pin compatible with THine THC63LVD103
鈥?/div>
Wide pixel clock range: 8 - 135 MHz
鈥?/div>
Guaranteed operation over
-20 to +85擄 C
ambient
temperature
鈥?/div>
Supports a wide range of video and graphics modes
including VGA, SVGA, XGA, SXGA, SXGA+, NTSC,
PAL, SDTV, and HDTV up to 1080I or 720P
鈥?/div>
Internal PLL requires no external loop filter
鈥?/div>
Selectable rising or falling clock edge for data
alignment
鈥?/div>
Compatible with Spread Spectrum clock source
鈥?/div>
Reduced LVDS output voltage swing mode
(selectable) to minimize EMI
鈥?/div>
CMOS/TTL data inputs can be configured for
reduced input voltage swing
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
Single 3.3 V supply
Low power consumption CMOS design
Power down mode
64-pin TQFP lead free package
Block Diagram
TA0-6
TB0-6
TC0-6
TD0-6
TE0-6
RS
R/F
/PWDN
7
7
7
7
7
TA+
TA-
TB+
TB-
Parallel
to Serial
TC+
TC-
TD+
TD-
TE+
TE-
CLKIN
(8 to 135 MHz)
PLL
TCLK+
TCLK-
V103A Datasheet
1
11/18/05
Revision 3.2
I n t e g r a t e d C i r c u i t S y s t e m s 鈥?5 2 5 R a c e St r e e t , S a n J o s e , C A 9 5 1 2 6 鈥?t e l ( 4 0 8) 2 97 - 1 2 0 1 鈥?w ww. i c s t . co m

V103AYLFT 產(chǎn)品屬性

  • V103A

  • Product Discontinuation 30/Jul/2012

  • 500

  • 集成電路 (IC)

  • 接口 - 驅(qū)動器，接收器，收發(fā)器

  • -

  • 發(fā)射器

  • -

  • LVDS

  • 3 V ~ 3.6 V

  • 表面貼裝

  • 64-VFQFP

  • 64-TQFP（10x10）

  • 帶卷 (TR)

V103AYLFT相關(guān)型號PDF文件下載

  • 型號
    版本
    描述
    廠商
    下載
  • 英文版
    TRIPLE 10-BIT LVDS TRANSMITTER FOR VIDEO
    ICST [Inte...
  • 英文版
    TRIPLE 10-BIT LVDS TRANSMITTER FOR VIDEO
    ICS
  • 英文版
    TRIPLE 10-BIT LVDS TRANSMITTER FOR VIDEO
    ICST [Inte...
  • 英文版
    TRIPLE 10-BIT LVDS TRANSMITTER FOR VIDEO
    ICST [Inte...
  • 英文版
    TRIPLE 10-BIT LVDS TRANSMITTER FOR VIDEO
    ICS
  • 英文版
    TRIPLE 10-BIT LVDS TRANSMITTER FOR VIDEO
    ICST [Inte...
  • 英文版
    TRIPLE 10-BIT LVDS TRANSMITTER FOR VIDEO
    ICST [Inte...
  • 英文版
    TRIPLE 10-BIT LVDS TRANSMITTER FOR VIDEO
    ICS
  • 英文版
    TRIPLE 10-BIT LVDS TRANSMITTER FOR VIDEO
    ICST [Inte...

您可能感興趣的PDF文件資料

掃碼下載APP，
一鍵連接廣大的電子世界。

在線人工客服

買家服務(wù)：
賣家服務(wù)：
技術(shù)客服：

0571-85317607

網(wǎng)站技術(shù)支持

13606545031

客服在線時(shí)間周一至周五
9:00-17:30

關(guān)注官方微信號，
第一時(shí)間獲取資訊。

建議反饋

聯(lián)系人：

聯(lián)系方式：

按住滑塊，拖拽到最右邊
>>
感謝您向阿庫提出的寶貴意見，您的參與是維庫提升服務(wù)的動力！意見一經(jīng)采納，將有感恩紅包奉上哦！