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SST89E516RD Datasheet

  • SST89E516RD

  • FlashFlex51 MCU

  • 932.00KB

  • 80頁

  • SST   SST

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FlashFlex MCU
SST89E516RD2 / SST89E516RD
SST89V516RD2 / SST89V516RD
Data Sheet
FEATURES:
鈥?8-bit 8051-Compatible Microcontroller (MCU)
with Embedded SuperFlash Memory
鈥?Fully Software Compatible
鈥?Development Toolset Compatible
鈥?Pin-For-Pin Package Compatible
鈥?SST89E516RD2 Operation
鈥?0 to 40 MHz at 5V
鈥?SST89V516RD2 Operation
鈥?0 to 33 MHz at 3V
鈥?1 KByte Internal RAM
鈥?Dual Block SuperFlash EEPROM
鈥?64 KByte primary block +
8 KByte secondary block
(128-Byte sector size for both blocks)
鈥?Individual Block Security Lock with SoftLock
鈥?Concurrent Operation during
In-Application Programming (IAP)
鈥?Memory Overlay for Interrupt Support during IAP
鈥?Support External Address Range up to 64
KByte of Program and Data Memory
鈥?Three High-Current Drive Ports (16 mA each)
鈥?Three 16-bit Timers/Counters
鈥?Full-Duplex, Enhanced UART
鈥?Framing Error Detection
鈥?Automatic Address Recognition
鈥?Ten Interrupt Sources at 4 Priority Levels
鈥?Four External Interrupt Inputs
鈥?Programmable Watchdog Timer (WDT)
鈥?Programmable Counter Array (PCA)
鈥?Four 8-bit I/O Ports (32 I/O Pins) and
One 4-bit Port
鈥?Second DPTR register
鈥?Low EMI Mode (Inhibit ALE)
鈥?SPI Serial Interface
鈥?Standard 12 Clocks per cycle, the device has an
option to double the speed to 6 clocks per cycle.
鈥?TTL- and CMOS-Compatible Logic Levels
鈥?Brown-out Detection
鈥?Low Power Modes
鈥?Power-down Mode with External Interrupt Wake-up
鈥?Idle Mode
鈥?Temperature Ranges:
鈥?Commercial (0擄C to +70擄C)
鈥?Industrial (-40擄C to +85擄C)
鈥?Packages Available
鈥?40-contact WQFN (Port 4 feature not available)
鈥?44-lead PLCC
鈥?40-pin PDIP (Port 4 feature not available)
鈥?44-lead TQFP
鈥?All non-Pb (lead-free) devices are RoHS compliant
PRODUCT DESCRIPTION
The SST89E516RDx and SST89V516RDx are members
of the FlashFlex family of 8-bit microcontroller products
designed and manufactured with SST鈥檚 patented and pro-
prietary SuperFlash CMOS semiconductor process tech-
nology. The split-gate cell design and thick-oxide tunneling
injector offer significant cost and reliability benefits for SST鈥檚
customers. The devices use the 8051 instruction set and
are pin-for-pin compatible with standard 8051 microcontrol-
ler devices.
The devices come with 72 KByte of on-chip flash
EEPROM program memory which is partitioned into 2
independent program memory blocks. The primary Block 0
occupies 64 KByte of internal program memory space and
the secondary Block 1 occupies 8 KByte of internal pro-
gram memory space.
The 8-KByte secondary block can be mapped to the lowest
location of the 64 KByte address space; it can also be hid-
den from the program counter and used as an independent
EEPROM-like data memory.
漏2007 Silicon Storage Technology, Inc.
S71273-03-000
1/07
1
In addition to the 72 KByte of EEPROM program memory
on-chip and 1024 x8 bits of on-chip RAM, the devices can
address up to 64 KByte of external program memory
andup to 64 KByte of external RAM.
The flash memory blocks can be programmed via a stan-
dard 87C5x OTP EPROM programmer fitted with a special
adapter and the firmware for SST鈥檚 devices. During power-
on reset, the devices can be configured as either a slave to
an external host for source code storage or a master to an
external host for an in-application programming (IAP) oper-
ation. The devices are designed to be programmed in-sys-
tem and in-application on the printed circuit board for
maximum flexibility. The devices are pre-programmed with
an example of the bootstrap loader in the memory, demon-
strating the initial user program code loading or subsequent
user code updating via the IAP operation. The sample
bootstrap loader is available for the user鈥檚 reference and
convenience only; SST does not guarantee its functionality
or usefulness. Chip-Erase or Block-Erase operations will
erase the pre-programmed sample code.
The SST logo, SuperFlash, and FlashFlex are registered trademarks of Silicon Storage Technology, Inc.
These specifications are subject to change without notice.

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