MM74HC273 Octal D-Type Flip-Flops with Clear
September 1983
Revised February 1999
MM74HC273
Octal D-Type Flip-Flops with Clear
General Description
The MM74HC273 edge triggered flip-flops utilize advanced
silicon-gate CMOS technology to implement D-type flip-
flops. They possess high noise immunity, low power, and
speeds comparable to low power Schottky TTL circuits.
This device contains 8 master-slave flip-flops with a com-
mon clock and common clear. Data on the D input having
the specified setup and hold times is transferred to the Q
output on the LOW-to-HIGH transition of the CLOCK input.
The CLEAR input when LOW, sets all outputs to a low
state.
Each output can drive 10 low power Schottky TTL equiva-
lent loads. The MM74HC273 is functionally as well as pin
compatible to the 74LS273. All inputs are protected from
damage due to static discharge by diodes to V
CC
and
ground.
Features
s
Typical propagation delay: 18 ns
s
Wide operating voltage range
s
Low input current: 1
碌A(chǔ)
maximum
s
Low quiescent current: 80
碌A(chǔ)
(74 Series)
s
Output drive: 10 LS-TTL loads
Ordering Code:
Order Number
MM74HC273M
MM74HC273SJ
MM74HC273MTC
MM74HC273N
Package Number
M20B
M20D
MTC20
N20A
Package Description
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-153, 0.300鈥?Wide
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300鈥?Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter 鈥淴鈥?to the ordering code.
Connection Diagram
Pin Assignments for DIP, SOIC, SOP and TSSOP
Top View
漏 1999 Fairchild Semiconductor Corporation
DS005331.prf
www.fairchildsemi.com