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MAX3892 Datasheet

  • MAX3892

  • " +3.3V, 2.5Gbps/2.7Gbps, SDH/SONET 4:1 Serializer with Cloc...

  • 331.16KB

  • Maxim   Maxim

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19-2215; Rev 0; 11/01
+3.3V, 2.5Gbps/2.7Gbps, SDH/SONET 4:1
Serializer with Clock Synthesis
General Description
The MAX3892 serializer is ideal for converting 4-bit-
wide, 622Mbps parallel data to 2.5Gbps serial data in
DWDM and SONET/SDH applications. A 4
鉁?/div>
4-bit FIFO
allows for any static delay between the parallel output
clock and parallel input clock. Delay variation up to a
unit interval (UI) is allowed after reset. A fully integrated
phase-locked loop (PLL) synthesizes an internal
2.5GHz serial clock from a 622MHz, 155.5MHz,
77.8MHz, or 38.9MHz reference clock. A selectable
dual VCO allows excellent jitter performance at both
SONET and forward-error correction (FEC) data rates.
Operating from a single 3.3V supply, this device
accepts low-voltage differential-signal (LVDS) clock
and data inputs for interfacing with high-speed digital
circuitry, and delivers current-mode logic (CML) serial
data and clock outputs. A loopback data output is pro-
vided to facilitate system diagnostic testing. The
MAX3892 is available in the extended temperature
range (-40擄C to +85擄C) in a 44-pin QFN package.
o
Single +3.3V Supply
o
455mW Power Consumption
o
1.4ps
RMS
Maximum Jitter Generation
o
4
鉁?/div>
4-Bit FIFO Input Buffer
o
622Mbps/666Mbps Parallel to 2.5Gbps/2.7Gbps
Serial Conversion
o
622MHz/667MHz or 311MHz/333MHz Clock Input
o
On-Chip Clock Synthesizer
o
Multiple Clock Reference Frequencies:
(622.08MHz, 155.52MHz, 77.76MHz, 38.88MHz) or
(666.51MHz, 166.63MHz, 83.31MHz, 41.66MHz)
o
LVDS Parallel Clock and Data Inputs
o
CML Serial Data and Clock Outputs
o
Additional CML Output for System Loopback
Testing
Features
MAX3892
Applications
SONET/SDH OC-48 Transmission Systems
WDM Transponders
Add/Drop Multiplexers
Dense Digital Cross-Connects
Backplane Interconnects
Ordering Information
PART
MAX3892EGH
TEMP. RANGE
-40擄C to +85擄C
PIN-PACKAGE
44 QFN-EP*
*EP
= exposed pad
Typical Application Circuit
LVPECL
100鈩?/div>
C
Z
V
CC
V
CC
RCLK-
LVDS
PDI0+
PDI0-
SONET/SDH
FRAMER
RCLK+ FIL
V
CC
CLKSET MODE RATESET
SDO+
SDO-
CML
MAX3273
CML
SCLKO+
SCLKO-
SLBEN
LASER
DRIVER
TTL
CML
PDI3+
PDI3-
MAX3892
LVDS
PCLKI+
PCLKI-
LVDS
PCLKO+
PCLKO-
RESET
FIFOERROR
SLBPD
SLBO+
SLBO-
MAX3882
鈥?/div>
OPTIONAL
FOR
SYSTEM
LOOPBACK
TEST
1:4 DESERIALIZER
WITH CDR
LOL
鈥?Future product
THIS SYMBOL REPRESENTS A TRANSMISSION
LINE OF CHARACTERISTIC IMPEDANCE Z
O
= 50鈩?
________________________________________________________________
Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim鈥檚 website at www.maxim-ic.com.

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