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L29C521PC22 Datasheet

  • L29C521PC22

  • 4 x 8-bit Multilevel Pipeline Register

  • 190.81KB

  • 8頁

  • LOGIC

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L29C520/521
DEVICES INCORPORATED
4 x 8-bit Multilevel Pipeline Register
L29C520/521
DEVICES INCORPORATED
4 x 8-bit Multilevel Pipeline Register
DESCRIPTION
The
L29C520
and
L29C521
are pin-
for-pin compatible with the
IDT29FCT520/IDT29FCT521 and
AMD Am29520/Am29521, imple-
mented in low power CMOS.
The L29C520 and L29C521 contain
four registers which can be configured
as two independent, 2-level pipelines
or as one 4-level pipeline.
The Instruction pins, I
1-0
, control the
loading of the registers. For either
device, the registers may be config-
ured as a four-stage delay line, with
data loaded into R1 and shifted
sequentially through R2, R3, and R4.
Also, for the L29C520, data may be
loaded from the inputs into either R1
or R3 with only R2 or R4 shifting. The
L29C521 differs from the L29C520 in
that R2 and R4 remain unchanged
during this type of data load, as
shown in Tables 1 and 2. Finally, I
1-0
may be set to prevent any register
from changing.
The S
1-0
select lines control a 4-to-1
multiplexer which routes the contents
of any of the registers to the Y output
pins. The independence of the I and S
controls allows simultaneous write
and read operations on different
registers.
FEATURES
u
Four 8-bit Registers
u
Implements Double 2-Stage Pipeline
or Single 4-Stage Pipeline Register
u
Hold, Shift, and Load Instructions
u
Separate Data In and Data Out Pins
u
High-Speed, Low Power CMOS
Technology
u
Three-State Outputs
u
Replaces IDT29FCT520/IDT29FCT521
and AMD Am29520/Am29521
u
Package Styles Available:
鈥?24-pin PDIP
鈥?28-pin PLCC, J-Lead
T
ABLE
1.
L29C520 I
NSTRUCTION
T
ABLE
I
1
L
L
H
H
I
0
L
H
L
H
Description
D漏R1
HOLD
D漏R1
R1漏R2
HOLD
R1漏R2
R2漏R3
D漏R3
HOLD
R3漏R4
R3漏R4
HOLD
ALL REGISTERS ON HOLD
T
ABLE
2.
L29C521 I
NSTRUCTION
T
ABLE
I
1
L
L
H
I
0
L
H
L
H
Description
D漏R1
HOLD
D漏R1
R1漏R2
HOLD
HOLD
R2漏R3
D漏R3
HOLD
R3漏R4
HOLD
HOLD
L29C520/521 B
LOCK
D
IAGRAM
H
ALL REGISTERS ON HOLD
T
ABLE
3.
REGISTER 1
REGISTER 2
O
UTPUT
S
ELECT
S
1
S
0
MUX
Register Selected
Register 4
Register 3
Register 2
Register 1
8
D
8-0
L
L
REG 1
REG 2
REG 3
REG 4
L
H
L
H
H
MUX
8
Y
7-0
OE
2
H
REGISTER 3
REGISTER 4
S
1-0
2
I
1-0
CLK
Pipeline Registers
1
08/02/2000鈥揕DS.520/1-P

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