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ISPPAC30-01PI Datasheet

  • ISPPAC30-01PI

  • Lattice Semiconductor [In-System Programmable Analog Circui...

  • 375.46KB

  • LATTICE   LATTICE

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ispPAC30
In-System Programmable Analog Circuit
October 2001
Preliminary Data Sheet
Features
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Flexible Interface and Programming Control
鈥?/div>
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Full con鏗乬uration capability, SPI or JTAG modes
Unlimited device updates using SRAM register
E
2
CMOS
廬
for non-volatile con鏗乬uration storage
Real-time microcontroller con鏗乬uration/control
High impedance: differential or single-ended
0V to 2.8V with programmable gains (鹵1 to 鹵10)
Dual multiplexers (pin or serial port controlled)
Connects easily to existing system circuits
Single-ended, 0V to 5V output swing
Gain bandwidth product >15MHz
Ampli鏗乪r, 鏗乴ter, integrator or comparator modes
7 鏗乴ter frequencies (50kHz to 600kHz)
Functional Block Diagram
IN1+ 13
IN1- 14
Vref1
12 VS
11 ENSPI
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Four Input Instrumentation Ampli鏗乪rs (IA鈥檚)
IA
IN2+ 15
Input/Output Routing Pool
Summation Routing Pool
OA
IA
MDAC
Filter
Amplify
Integrate
Compare
10 TMS
9 TDO
8 TDI
7 TCK
6 CS
IN2- 16
VREFOUT
17
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Two Con鏗乬urable Rail-to-Rail Output Amps
OUT1 18
OUT2 19
SCOM 20
IN3+ 21
MDAC
IA
OA
IA
Filter
Amplify
Integrate
Compare
5 MSEL1
4 MSEL2
3 CAL
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Two, 4-Quadrant 8-Bit Multiplying DAC鈥檚
鈥?Full bandwidth when used as a multiplier
鈥?Precision gain (<0.01 steps) with signal as input
鈥?Precision offset (in 7 ranges) using internal Vref
Vref2
IN3- 22
IN4+ 23
IN4- 24
JTAG/SPI
Interface Logic
& Configuration
Memory
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Analog Input/Summation Routing Pools
鈥?/div>
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Routing of all I/O to any IA or MDAC
Any IA/MDAC summed to either output ampli鏗乪r
Circuits with and without feedback possible
Routable to maintain pin location relationships
Single supply (+5V) operation
Precision voltage reference output (2.5V)
Power-down for
碌
Watt power consumption
Auto-calibration of internal offsets
Available in 28-pin PDIP or 24-pin SOIC
Recon鏗乬urable or adaptive signal conditioning
Analog front end for most A/D converters
Programmable analog signal control loops
Precision programmable gain ampli鏗乪rs
Auto-Calibration
2.5V Reference
2 PD
1 GND
ispPAC30 24-Pin SOIC
鈻?/div>
Other Product Features
Description
The ispPAC
廬
30 is a member of the Lattice family of In-
System Programmable (ISP鈩? analog integrated cir-
cuits. It is digitally con鏗乬ured via SRAM and utilizes
E
2
CMOS memory for non-volatile storage of its con鏗乬u-
ration. The 鏗俥xibility of ISP enables programming, veri鏗?
cation and unlimited recon鏗乬uration, directly on the
printed circuit board.
The ispPAC30 is a complete front end solution for data
acquisition applications using 10 to 12-bit ADC's. It pro-
vides multiple single-ended or differential signal inputs,
multiplexing, precision gain, offset adjustment, 鏗乴tering,
and comparison functionality. It also has complete
routability of inputs or outputs to any input cell and then
from any input cell to either summing node of the two
output ampli鏗乪rs. Designers con鏗乬ure the ispPAC30
and verify its performance using PAC-Designer
廬
, an
easy to use, Microsoft Windows
廬
compatible develop-
ment tool. Device programming is supported using PC
parallel port I/O operations.
1
pac30_01
鈻?/div>
Applications
Vin1
Vin2
Vin3
ispPAC30
Dual
12-Bit
ADC
碌Controller
www.latticesemi.com

ISPPAC30-01PI 產(chǎn)品屬性

  • Lattice

  • SPLD - 簡單可編程邏輯器件

  • ISPPA

  • 7 ns

  • 3 V to 3.6 V

  • + 85 C

  • - 40 C

  • PDIP-28

  • Through Hole

  • 13

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