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IDT72605 Datasheet

  • IDT72605

  • CMOS SyncBiFIFO?

  • IDT

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CMOS SyncBiFIFO
鈩?/div>
256 x 18 x 2 and 512 x 18 x 2
Integrated Device Technology, Inc.
IDT72605
IDT72615
FEATURES:
鈥?Two independent FIFO memories for fully bidirectional
data transfers
鈥?256 x 18 x 2 organization (IDT 72605)
鈥?512 x 18 x 2 organization (IDT 72615)
鈥?Synchronous interface for fast (20ns) read and write
cycle times
鈥?Each data port has an independent clock and read/write
control
鈥?Output enable is provided on each port as a three-state
control of the data bus
鈥?Built-in bypass path for direct data transfer between two
ports
鈥?Two fixed flags, Empty and Full, for both the A-to-B and
the B-to-A FIFO
鈥?Programmable flag offset can be set to any depth in the
FIFO
鈥?The synchronous BiFIFO is packaged in a 64-pin TQFP
(Thin Quad Flatpack), 68-pin PGA and 68-pin PLCC
鈥?Industrial temperature range (-40oC to +85oC) is avail-
able, tested to military electrical specifications
DESCRIPTION:
The IDT72605 and IDT72615 are very high-speed, low-
power bidirectional First-In, First-Out (FIFO) memories, with
synchronous interface for fast read and write cycle times. The
SyncBiFIFO鈩?is a data buffer that can store or retrieve
information from two sources simultaneously. Two Dual-Port
FIFO memory arrays are contained in the SyncBiFIFO; one
data buffer for each direction.
The SyncBiFIFO has registers on all inputs and outputs.
Data is only transferred into the I/O registers on clock edges,
hence the interfaces are synchronous. Each Port has its own
independent clock. Data transfers to the I/O registers are
gated by the enable signals. The transfer direction for each
port is controlled independently by a read/write signal. Individ-
ual output enable signals control whether the SyncBiFIFO is
driving the data lines of a port or whether those data lines are
in a high-impedance state.
Bypass control allows data to be directly transferred from
input to output register in either direction.
The SyncBiFIFO has eight flags. The flag pins are full,
empty, almost-full, and almost-empty for both FIFO memo-
ries. The offset depths of the almost-full and almost-empty
flags can be programmed to any location.
The SyncBiFIFO is fabricated using IDT鈥檚 high-speed,
submicron CMOS technology.
FUNCTIONAL BLOCK DIAGRAM
D
A0
-D
A17
R/
W
A
EN
A
OE
A
HIGH
Z
CONTROL
CLK
A
INPUT REGISTER
OUTPUT REGISTER
MUX
MEMORY
ARRAY
512 x 18
256 x 18
MUX
MEMORY
ARRAY
512 x 18
256 x 18
RESET
LOGIC
CS
A
A
2
A
1
A
0
碌
P
INTERFACE
FLAG
LOGIC
RS
EF
BA
PAE
BA
PAF
BA
FF
BA
3
7
EF
AB
PAE
AB
PAF
AB
FF
AB
FLAG
LOGIC
POWER
SUPPLY
INPUT REGISTER
V
CC
GND
CLK
B
OUTPUT REGISTER
HIGH
Z
CONTROL
OE
B
R/
W
B
EN
B
BYP
B
COMMERCIAL TEMPERATURE RANGES
漏1996
Integrated Device Technology, Inc.
D
B0
-D
B17
2704 drw 01
SyncBiFIFO is a trademark and the IDT logo is a registered trademark of Integrated Device Technology, Inc.
DECEMBER 1996
DSC-2704/5
For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391.
5.18
1

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