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CY7C4291 Datasheet

  • CY7C4291

  • 64K/128Kx9 Deep Sync FIFOs

  • Cypress

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CY7C4281 CY7C429164K/128K x 9 Deep Sync FIFOs
CY7C4281
CY7C4291
64K/128K x 9 Deep Sync FIFOs
Features
鈥?High-speed, low-power, first-in first-out (FIFO)
memories
鈥?64K 脳 9 (CY7C4281)
鈥?128K 脳 9 (CY7C4291)
鈥?0.5-micron CMOS for optimum speed/power
鈥?High-speed 100-MHz operation (10-ns read/write cycle
times)
鈥?Low power
鈥?I
CC
= 40 mA
鈥?/div>
I
SB
= 2 mA
鈥?Fully asynchronous and simultaneous read and write
operation
鈥?Empty, Full, and programmable Almost Empty and
Almost Full status flags
鈥?TTL compatible
鈥?Output Enable (OE) pin
鈥?Independent read and write enable pins
鈥?Center power and ground pins for reduced noise
鈥?Supports free-running 50% duty cycle clock inputs
鈥?Width Expansion Capability
鈥?Pin-compatible density upgrade to CY7C42X1
family
鈥?Pin-compatible density upgrade to
IDT72201/11/21/31/41/51
鈥?Pb-Free Packages Available
Functional Description
The CY7C4281/91 are high-speed, low-power FIFO
memories with clocked read and write interfaces. All are nine
bits wide. The CY7C4281/91 are pin-compatible to the
CY7C42X1 Synchronous FIFO family. Programmable
features include Almost Full/Almost Empty flags. These FIFOs
provide solutions for a wide variety of data buffering needs,
including high-speed data acquisition, multiprocessor inter-
faces, and communications buffering.
These FIFOs have nine-bit input and output ports that are
controlled by separate clock and enable signals. The input port
is controlled by a free-running clock (WCLK) and two
write-enable pins (WEN1, WEN2/LD).
When WEN1 is LOW and WEN2/LD is HIGH, data is written
into the FIFO on the rising edge of the WCLK signal. While
WEN1, WEN2/LD is held active, data is continually written into
the FIFO on each WCLK cycle. The output port is controlled in
a similar manner by a free-running read clock (RCLK) and two
read enable pins (REN1, REN2). In addition, the
CY7C4281/91 has an output enable pin (OE). The read
(RCLK) and write (WCLK) clocks may be tied together for
single-clock operation or the two clocks may be run indepen-
dently for asynchronous read/write applications. Clock
frequencies up to 100 MHz are achievable. Depth expansion
is possible using one enable input for system control, while the
other enable is controlled by expansion logic to direct the flow
of data.
Logic Block Diagram
D
0鈥?
Pin Configuration
PLCC
Top View
D
2
D
3
D
4
D
5
D
6
D
7
D
8
INPUT
REGISTER
WCLK WEN1 WEN2/LD
FLAG
PROGRAM
REGISTER
WRITE
CONTROL
EF
Dual Port
RAMARRAY
64K x 9
128K x 9
FLAG
LOGIC
PAE
PAF
FF
READ
POINTER
D
1
D
0
PAF
PAE
GND
REN1
RCLK
REN2
OE
5
6
7
8
9
10
11
12
13
4 3 2 1 32 31 30
29
28
25
24
23
22
21
14 15 16 17 18 19 20
EF
FF
Q
0
Q
1
Q
2
Q
3
Q
4
CY7C4281
CY7C4291
27
26
RS
WEN1
WCLK
WEN2/LD
V
CC
Q
8
Q
7
Q
6
Q
5
WRITE
POINTER
RS
RESET
LOGIC
THREE-STATE
OUTPUT REGISTER
OE
Q
0鈥?
READ
CONTROL
RCLK REN1 REN2
Cypress Semiconductor Corporation
Document #: 38-06007 Rev. *C
鈥?/div>
3901 North First Street
鈥?/div>
San Jose
,
CA 95134
鈥?/div>
408-943-2600
Revised August 2, 2005

CY7C4291相關(guān)型號PDF文件下載

  • 型號
    版本
    描述
    廠商
    下載
  • 英文版
    16K x 8/9 Dual-Port Static RAM with Sem, Int, Busy
    Cypress
  • 英文版
    32K x 8/9 Dual-Port Static RAM
    Cypress
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    16K x 8/9 Dual-Port Static RAM with Sem, Int, Busy
    Cypress
  • 英文版
    32K x 8/9 Dual-Port Static RAM
    Cypress
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with SEM, INT...
    CYPRESS
  • 英文版
    4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with SEM, INT...
    CYPRESS [C...
  • 英文版
    4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with Sem, Int...
    Cypress
  • 英文版
    16K x 16/18 Dual-Port Static RAM
    Cypress
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS [C...

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