PRELIMINARY
CY7C1304CV25
9-Mbit Burst of 4 Pipelined SRAM with QDR鈩?Architecture
Features
鈥?Separate independent Read and Write data ports
鈥?Supports concurrent transactions
鈥?167-MHz Clock for high bandwidth
鈥?2.5 ns Clock-to-Valid access time
鈥?4-Word Burst for reducing the address bus frequency
鈥?Double Data Rate (DDR) interfaces on both Read and
Write Ports (data transferred at 333 MHz) @167 MHz
鈥?Two input clocks (K and K) for precise DDR timing
鈥?SRAM uses rising edges only
鈥?Two output clocks (C and C) account for clock skew
and flight time mismatching
鈥?Single multiplexed address input bus latches address
inputs for both Read and Write ports
鈥?Separate Port Selects for depth expansion
鈥?Synchronous internally self-timed writes
鈥?2.5V core power supply with HSTL Inputs and Outputs
鈥?13 x 15 x 1.4 mm 1.0-mm pitch fBGA package, 165-ball
(11x15 matrix)
鈥?Variable drive HSTL output buffers
鈥?Expanded HSTL output voltage (1.4V鈥?.9V)
鈥?JTAG 1149.1 compatible test access port
Functional Description
The CY7C1304CV25 is a 2.5V Synchronous Pipelined SRAM
equipped with QDR鈩?architecture. QDR architecture consists
of two separate ports to access the memory array. The Read
port has dedicated Data Outputs to support Read operations
and the Write port has dedicated Data Inputs to support Write
operations. QDR architecture has separate data inputs and
data outputs to completely eliminate the need to 鈥渢urn-around鈥?/div>
the data bus required with common I/O devices. Access to
each port is accomplished through a common address bus.
Addresses for Read and Write addresses are latched on
alternate rising edges of the input (K) clock. Accesses to the
device鈥檚 Read and Write ports are completely independent of
one another. In order to maximize data throughput, both Read
and Write ports are equipped with Double Data Rate (DDR)
interfaces. Each address location is associated with four 18-bit
words. Since data can be transferred into and out of the device
on every rising edge of both input clock (K/K and C/C) memory
bandwidth is maximized while simplifying system design by
eliminating bus 鈥渢urn-arounds.鈥?/div>
Depth expansion is accomplished with Port Selects for each
port. Port selects allow each port to operate independently.
All synchronous inputs pass through input registers controlled
by the K or K input clocks. All data outputs pass through output
registers controlled by the C or C input clocks. Writes are
conducted with on-chip synchronous self-timed write circuitry.
Configurations
CY7C1304CV25 鈥?512K x 18
Logic Block Diagram (CY7C1304CV25)
D
[17:0]
18
Write Write Write Write
Reg
Reg Reg Reg
Read Add. Decode
Write Add. Decode
A
(16:0)
Address
Register
17
Address
Register
128Kx18 Array
128Kx18 Array
128Kx18 Array
128Kx18 Array
17
A
(16:0)
K
K
CLK
Gen.
Control
Logic
RPS
C
C
Read Data Reg.
Vref
WPS
BWS
[0:1]
72
Control
Logic
36
36
Reg.
Reg.
18
Reg.
18
Q
[17:0]
Cypress Semiconductor Corporation
Document #: 38-05494 Rev. *A
鈥?/div>
3901 North First Street
鈥?/div>
San Jose
,
CA 95134
鈥?/div>
408-943-2600
Revised June 1, 2004
CY7C1304CV25 PDF文件相關(guān)型號(hào)
CY7C1304CV25-167BZC
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英文版
16K x 8/9 Dual-Port Static RAM with Sem, Int, Busy
Cypress
-
英文版
32K x 8/9 Dual-Port Static RAM
Cypress
-
英文版
64K/128K x 8/9 Dual-Port Static RAM
CYPRESS
-
英文版
64K/128K x 8/9 Dual-Port Static RAM
CYPRESS [C...
-
英文版
64K/128K x 8/9 Dual-Port Static RAM
CYPRESS
-
英文版
64K/128K x 8/9 Dual-Port Static RAM
CYPRESS [C...
-
英文版
16K x 8/9 Dual-Port Static RAM with Sem, Int, Busy
Cypress
-
英文版
32K x 8/9 Dual-Port Static RAM
Cypress
-
英文版
64K/128K x 8/9 Dual-Port Static RAM
CYPRESS
-
英文版
64K/128K x 8/9 Dual-Port Static RAM
CYPRESS [C...
-
英文版
64K/128K x 8/9 Dual-Port Static RAM
CYPRESS
-
英文版
64K/128K x 8/9 Dual-Port Static RAM
CYPRESS [C...
-
英文版
4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with SEM, INT...
CYPRESS
-
英文版
4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with SEM, INT...
CYPRESS [C...
-
英文版
4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with Sem, Int...
Cypress
-
英文版
16K x 16/18 Dual-Port Static RAM
Cypress
-
英文版
32K/64K x 16/18 Dual-Port Static RAM
CYPRESS
-
英文版
32K/64K x 16/18 Dual-Port Static RAM
CYPRESS [C...
-
英文版
32K/64K x 16/18 Dual-Port Static RAM
CYPRESS
-
英文版
32K/64K x 16/18 Dual-Port Static RAM
CYPRESS [C...
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