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CY2CC810OXC Datasheet

  • CY2CC810OXC

  • 1:10 Clock Fanout Buffer

  • 8頁

  • CYPRESS

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CY2CC810
1:10 Clock Fanout Buffer
Features
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Low-voltage operation
V
DD
range from 2.5V to 3.3V
1:10 fanout
Over voltage tolerant input hot swappable
Drives either a 50-Ohm or 75-Ohm transmission line
Low-input capacitance
250 ps typical output-to-output skew
19 ps typical DJ jitter
Typical propagation delay < 3.5 ns
High-speed operation > 500 MHz
Industrial versions available
Available packages include: SOIC, SSOP
Description
The Cypress series of network circuits are produced using
advanced 0.35-micron CMOS technology, achieving the
industry鈥檚 fastest logic and buffers.
The Cypress CY2CC810 fanout buffer features one input and
ten outputs. Designed for data communications clock
management applications, the large fanout from a single input
reduces loading on the input clock.
AVCMOS-type outputs dynamically adjust for variable
impedance matching and reduce noise overall.
.
Block Diagram
Q1
Q2
Pin Configuration
IN
GND
Q1
VDD
Q2
GND
Q3
VDD
Q4
GND
CY2CC810
VD D
Q3
Q4
Q5
Q6
Q7
IN
INPUT
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
VDD
Q10
Q9
GND
Q8
VDD
Q7
GND
Q6
Q5
GND
Q8
Q9
Q 10
OUTPUT
(AVCMOS)
20 pin SOIC/SSOP
Pin Description
Pin Number
1
2, 6, 10, 13, 17
4, 8, 15, 20
3, 5, 7, 9, 11, 12, 14, 16, 18, 19
Pin Name
IN
GND
Input
Ground
Power Supply
Output
Description
LVCMOS
Power
Power
AVCMOS
V
DD
Q1... Q10
Cypress Semiconductor Corporation
Document #: 38-07056 Rev. *E
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198 Champion Court
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San Jose
,
CA 95134-1709
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408-943-2600
Revised September 5, 2006

CY2CC810OXC PDF文件相關(guān)型號

CY2CC810OXCT,CY2CC810OXI,CY2CC810OXIT

CY2CC810OXC 產(chǎn)品屬性

  • Obsolescence Notification Nov 2010

  • 66

  • 集成電路 (IC)

  • 時鐘/計時 - 時鐘緩沖器，驅(qū)動器

  • -

  • 扇出緩沖器（分配）

  • 1

  • 1:10

  • 無/無

  • LVCMOS

  • AVCMOS

  • 650MHz

  • 2.375 V ~ 3.465 V

  • 0°C ~ 70°C

  • 表面貼裝

  • 20-SSOP（0.209"，5.30mm 寬）

  • 20-SSOP

  • 管件

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