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CD74HCT75 Datasheet

  • CD74HCT75

  • High Speed CMOS Logic Dual 2-Bit Bistable Transparent Latch

  • 15頁

  • TI

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Data sheet acquired from Harris Semiconductor
SCHS135
CD74HC75,
CD74HCT75
Dual 2-Bit Bistable
Transparent Latch
at V
CC
= 5V
鈥?HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
V
IL
= 0.8V (Max), V
IH
= 2V (Min)
- CMOS Input Compatibility, I
l
鈮?/div>
1碌A(chǔ) at V
OL
, V
OH
March 1998
Features
鈥?True and Complementary Outputs
鈥?Buffered Inputs and Outputs
鈥?Fanout (Over Temperature Range)
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
鈥?Wide Operating Temperature Range . . . -55
o
C to 125
o
C
鈥?Balanced Propagation Delay and Transition Times
鈥?Signi鏗乧ant Power Reduction Compared to LSTTL
Logic ICs
鈥?HC Types
- 2V to 6V Operation
- High Noise Immunity: N
IL
= 30%, N
IH
= 30% of V
CC
[ /Title
(CD74
HC75,
CD74
HCT75
)
/Sub-
ject
(Dual
2-Bit
Bistabl
e
Description
The Harris CD74HC75 and CD74HCT75 are dual 2-bit
bistable transparent latches. Each one of the 2-bit latches is
controlled by separate Enable inputs (1E and 2E) which are
active LOW. When the Enable input is HIGH data enters the
latch and appears at the Q output. When the Enable input
(1E and 2E) is LOW the output is not affected.
Ordering Information
Pinout
CD74HC75, CD74HCT75
(PDIP, SOIC)
TOP VIEW
1Q0 1
1D0 2
1D1 3
2E 4
V
CC
5
2D0 6
2D1 7
2Q1 8
16 1Q0
15 1Q1
14 1Q1
13 1E
12 GND
11 2Q0
10 2Q0
9 2Q1
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright
漏
Harris Corporation 1998
File Number
1666.1
1

CD74HCT75 PDF文件相關(guān)型號(hào)

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