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BUS-8553 Datasheet

  • BUS-8553

  • ETC [MIL-STD-1553 TRANSCEIVER]

  • ETC

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BUS-65153
MIL-STD-1553B, NOTICE 2 AND MIL-STD-1760B
SMALL TERMINAL INTERFACE CIRCUIT 鈥淪TIC鈥?/div>
DESCRIPTION
The BUS-65153 is a complete, dual
redundant MIL-STD-1553B Remote
Terminal. Packaged in a 1.9" x 1.0" x
0.2", 70-pin ceramic package, the
BUS-65153 provides the transmitter
voltage level required by MIL-STD-
1760. Also in support of MIL-STD-
1760, the RT address inputs are
latchable.
The BUS-65153 contains two low power
transceivers and a DDC custom designed
chip. This chip includes dual
encoder/decoder, RT protocol logic, tri-
state data buffers, and DMA transfer con-
trol logic. The BUS-65153 supports all 13
dual redundant mode codes, any combi-
nation of which may be illegalized by an
external PROM, PLD, or RAM device.
Parallel data transfers are accomplished
via a DMA type interface. Both 8-bit and
16-bit transfers are supported.
The BUS-65153 can be easily inter-
faced to most CPU's. In addition, the
BUS-65153 can interface directly to
minimum complexity subsystems
such as switches, D/A converters,
etc.
The address bus and transfer control sig-
nals may be configured for either two-state
or three-state operation. Use of the three-
state address mode reduces the number
of external components required for a
DMA processor interface.
The input clock frequency is user
selectable for either 12 or 16 MHz. In the
12 MHz mode, the decoder operates at 24
MHz, providing superior word error rate
and zero crossing distortion tolerance. The
Busy, Service Request, and Subsystem
Flag RT Status Word bits are provided as
discrete pins, allowing for easy access by
the subsystem.
Various message timing and error
flag indicators are provided to facili-
tate the subsystem interface.
FEATURES
鈥?/div>
Supports MIL-STD-1553B Notice 2
and MIL-STD-1760 Stores
Management
鈥?/div>
Complete Integrated Remote
Terminal Including:
- Dual Low-Power Transceiver
- Complete RT Protocol Logic
鈥?/div>
Small, 70-Pin Ceramic Package
鈥?/div>
Meets 1553A/McAir Response Time
Requirements
鈥?/div>
Selectable 8/16-bit DMA Interface
鈥?/div>
Optional Tri-State Address Bus and
Transfer Control Signals
鈥?/div>
Direct Interface to Simple Systems
鈥?/div>
Selectable Input Clock, 12 or 16
MHz
鈥?/div>
MIL-PRF-38534 Processing
Available
UPPER DATA
BUFFER
TX/RX A
TRANSCEIVER
A
D15-D8
UPPER
DATA BUS
A DIR
A XF
55 ohms
BUS-25679
8
1
7
2
5
3
4
TX/RX A
DB_SEL
DT_REQ
DT_GRT
BUS A
A XF
A DIR
DATA BUS
WIDTH SELECT
TRANSMITTER
INHIBIT
TX_INH
55 ohms
B DIR
B XF
55 ohms
BUS-25679
8
7
5
4
1
2
3
1553
BUS
I/O
ENCODER/
DECODER AND
WATCHDOG
TIMER
TX/RX B
TRANSCEIVER
B
DMA HANDSHAKE
AND TRANSFER
CONTROL LOGIC
DT_ACK
DMA
HANDSHAKE
HS_FAIL
CS
WRT
BUS B
B XF
B DIR
55 ohms
TX/RX B
DATA
TRANSFER
CONTROL
ADDRESS
TRI-STATE
CONTROL
ADDR_ENA
CLOCK INPUT
AND
FREQUENCY
SELECT
CLK
CLK_SEL
LOWER DATA
BUFFER
D7-D0
LOWER
DATA BUS
RT_AD4-RT_AD0
R.T.
ADDRESS
RT_AD_P
RT_AD_ERR
RT_AD_LAT
R.T. ADDRESS
PARITY AND
COMPARE LOGIC
5
REGISTERS
AND
R.T. STATE
MACHINE
LOGIC
ADDRESS
BUFFERS
A13-A0
14-BIT
ADDRESS
BUS
*
NBGRT
INCMD
GBR
ME
RT_FAIL
RESET
RESET
ILLCMD
ILLEGALIZATION
AND STATUS
INPUTS
SERVICE_REQUEST
SSFLAG
BUSY
STATUS,
ILLEGALIZATION,
AND
TRANSMITTER
INHIBIT LOGIC
CURRENT COMMAND,
*
LAST COMMAND, STATUS,
AND BIT WORD
MESSAGE
TIMING
SIGNALS
Note: Transformers are external
FIGURE 1. BUS-65153 BLOCK DIAGRAM
漏
1991, 1999 Data Device Corporation

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