Philips Semiconductors
Product specification
TrenchMOS鈩?transistor
Standard level FET
GENERAL DESCRIPTION
N-channel enhancement mode
standard level field-effect power
transistor in a plastic envelope
suitable for surface mounting. Using
鈥檛rench鈥?technology the device
features very low on-state resistance
and has integral zener diodes giving
ESD protection up to 2kV. It is
intended for use in automotive and
general
purpose
switching
applications.
BUK7635-55
QUICK REFERENCE DATA
SYMBOL
V
DS
I
D
P
tot
T
j
R
DS(ON)
PARAMETER
Drain-source voltage
Drain current (DC)
Total power dissipation
Junction temperature
Drain-source on-state
resistance
V
GS
= 10 V
MAX.
55
34
85
175
35
UNIT
V
A
W
藲C
m鈩?/div>
PINNING - SOT404
PIN
1
2
3
mb
gate
drain
source
drain
DESCRIPTION
PIN CONFIGURATION
mb
SYMBOL
d
g
2
1
3
s
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL
V
DS
V
DGR
鹵V
GS
I
D
I
D
I
DM
P
tot
T
stg
, T
j
PARAMETER
Drain-source voltage
Drain-gate voltage
Gate-source voltage
Drain current (DC)
Drain current (DC)
Drain current (pulse peak value)
Total power dissipation
Storage & operating temperature
CONDITIONS
-
R
GS
= 20 k鈩?/div>
-
T
mb
= 25 藲C
T
mb
= 100 藲C
T
mb
= 25 藲C
T
mb
= 25 藲C
-
MIN.
-
-
-
-
-
-
-
- 55
MAX.
55
55
16
34
24
136
85
175
UNIT
V
V
V
A
A
A
W
藲C
ESD LIMITING VALUE
SYMBOL
V
C
PARAMETER
Electrostatic discharge capacitor
voltage, all pins
CONDITIONS
Human body model
(100 pF, 1.5 k鈩?
MIN.
-
MAX.
2
UNIT
kV
THERMAL RESISTANCES
SYMBOL
R
th j-mb
R
th j-a
PARAMETER
Thermal resistance junction to
mounting base
Thermal resistance junction to
ambient
CONDITIONS
-
Minimum footprint, FR4
board
TYP.
-
50
MAX.
1.75
-
UNIT
K/W
K/W
April 1998
1
Rev 1.100
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