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PRELIMINARY TECHNICAL DATA

a

Preliminary Technical Data

FEATURES

Guaranteed Monotonic

INL Error: 鹵4LSB max

On-Chip 1.25/2.5V, 10ppm/擄C Reference

Temperature Range: -40擄C to +85擄C

Rail to Rail Output Amplifier

Package Type: 100-lead LQFP (14mm x 14mm)

User Interfaces:

Parallel,

Serial (SPI, QSPI, Microwire and DSP compatible

featuring Data Readback)

I2C Compatible Interface

INTEGRATED FUNCTIONS

Channel Monitor

Simultaneous Output Update via

LDAC

Clear Function to User Programmable Code

Amplifier Boost Mode to Optimize Slew Rate

User Programmable Offset and Gain Adjust

Toggle Mode: Enables Squarewave Generation

40-Channel, 3V/5V Single Supply,

14-Bit, Voltage-Output DAC

AD5380

GENERAL DESCRIPTION

The AD5380 is a complete single supply, 40-channel, 14-

bit DAC available in 100-lead LQFP package. All

40-channels have an on-chip output amplifier with rail-to-

rail operation. The AD5380 includes an internal 1.25/

2.5V, 10ppm/擄C reference, an on-chip channel monitor

function that multiplexes the analog outputs to a common

MON_OUT pin for external monitoring and an output

amplifier boost mode that allows the amplifier settling

time to be optimized. The AD5380 contains a double

buffered parallel interface featuring a

WR

pulse width of

20ns, a serial interface compatible with SPI

TM

, QSPI

TM

,

MICROWIRE

TM

and DSP interface standards with

interface speeds in excess of 30MHz and an I2C

compatible interface supporting 400kHz data transfer rate.

An input register followed by a DAC register provides

double buffering allowing the DAC outputs to be updated

independantly or simultaneously using the

LDAC

input.

Each channel has a programmable gain and offset adjust

register allowing the user to fully calibrate any DAC Channel.

Power consumption is typically 0.3mA/channel.

APPLICATIONS

Variable Optical Attenuators (VOA)

Level Setting

Optical Microelectromechanical Systems (MEMs)

Control Systems

FUNCTIONAL BLOCK DIAGRAM

DVDD (X3)

PD

SER/PAR

FIFO EN

CS/(SYNC/AD0)

WR/(DCEN/AD1)

SDO(A/B)

DB13 /(DIN/SDA)

DB12 /(SCLK/SCL)

DB11 /(SPI/I2C)

DB10

.

DB0

A5

A0

REG0

REG1

RESET

BUSY

CLR

POWER-ON

RESET

DGND (X3) AVDD (X5)

AGND (X5)

DAC GND (X5)

REFGND

REFOUT/ REFIN SIGNAL GND (X5)

AD5380

14

INPUT

REG

0

2.5V

Reference

14

X

m REG0

c REG0

+

14

14

14

FIFO

+

STATE

MACHINE

+

CONTROL

LOGIC

DAC

14

REG

0

DAC 0

+

-

R

R

VOUT 0

INTERFACE

CONTROL

LOGIC

14

INPUT

REG

1

14

14

X

+

.

14

.

14

.

.

.

14

INPUT

REG

6

DAC

14

REG

1

DAC 1

.

.

.

DAC 6

+

-

R

m REG1

.

.

.

14

.

.

X

c REG1

.

.

.

.

.

VOUT 1

VOUT 2

R

.

.

.

+

-

VOUT 3

VOUT 4

VOUT 5

VOUT 6

14

+

14

14

DAC

14

REG

6

m REG6

c REG6

R

R

VOUT 0 .......... VOUT 38

14

INPUT

REG

7

14

14

X

+

39 -TO-1

MUX

14

14

DAC

14

REG

7

DAC 7

+

-

R

R

VOUT 7

VOUT 8

m REG7

c REG7

X5

LDAC

VOUT 38

VOUT 39 / MON_OUT

*Protected by U.S. Patent Nos. 5,969,657; other patents pending.

SPI

and

QSPI

are Trademarks of Motorola, Inc.

MICROWIRE

is a Trademark of National Semiconductor Corporation.

Information furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assumed by Analog Devices for its

use, nor for any infringements of patents or other rights of third parties

which may result from its use. No license is granted by implication or

otherwise under any patent or patent rights of Analog Devices.

REV. PrF 09/2003

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781/329-4700

World Wide Web Site: http://www.analog.com

Fax: 781/326-8703

漏 Analog Devices, Inc., 2003

next

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