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74VHCT573A Datasheet

  • 74VHCT573A

  • Octal D-Type Latch with 3-STATE Outputs

  • Fairchild

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74VHCT573A Octal D-Type Latch with 3-STATE Outputs
January 1998
Revised April 2005
74VHCT573A
Octal D-Type Latch with 3-STATE Outputs
General Description
The VHCT573A is an advanced high speed CMOS octal
latch with 3-STATE output fabricated with silicon gate
CMOS technology. It achieves the high speed operation
similar to equivalent Bipolar Schottky TTL while maintain-
ing the CMOS low power dissipation. This 8-bit D-type
latch is controlled by a Latch Enable input (LE) and an Out-
put Enable input (OE). When the OE input is HIGH, the
eight outputs are in a high impedance state.
Protection circuits ensure that 0V to 7V can be applied to
the input and output (Note 1) pins without regard to the
supply voltage. This device can be used to interface 3V to
5V systems and two supply systems such as battery back
up. This circuit prevents device destruction due to mis-
matched supply and input voltages.
Note 1:
Outputs in OFF-State.
Features
s
High speed: t
PD
7.7 ns (typ) at T
A
2.0V, V
IL
25
q
C
0.8V
s
High Noise Immunity: V
IH
s
Power Down Protection is provided on all inputs and
outputs
s
Low Noise: V
OLP
1.6V (max)
25
q
C
s
Low Power Dissipation:
I
CC
4
P
A (max) @ T
A
s
Pin and function compatible with 74HCT573
Ordering Code:
Order Number
74VHCT573AM
74VHCT573ASJ
74VHCT573AMTC
74VHCT573AN
Package Number
M20B
M20D
MTC20
N20A
Package Description
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter 鈥淴鈥?to the ordering code.
Pb-Free package per JEDEC J-STD-020B.
Logic Symbol
IEEE/IEC
Connection Diagram
漏 2005 Fairchild Semiconductor Corporation
DS500028
www.fairchildsemi.com

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