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74ABT823 Datasheet

  • 74ABT823

  • 9-bit D-type flip-flop with reset and enable

  • 56.92KB

  • Philips

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Philips Semiconductors
Product specification
9-bit D-type flip-flop with reset and enable
(3-State)
74ABT823
FEATURES
flip-flops
鈥?/div>
High speed parallel registers with positive edge-triggered D-type
鈥?/div>
Ideal where high speed, light loading, or increased fan-in are
required with MOS microprocessors
DESCRIPTION
The 74ABT823 Bus interface Register is designed to eliminate the
extra packages required to buffer existing registers and provide
extra data width for wider data/address paths of buses carrying
parity.
The 74ABT823 is a 9-bit wide buffered register with Clock Enable
(CE) and Master Reset (MR) which are ideal for parity bus
interfacing in high microprogrammed systems.
The register is fully edge-triggered. The state of each D input, one
set-up time before the Low-to-High clock transition is transferred to
the corresponding flip-flop鈥檚 Q output.
鈥?/div>
Output capability: +64mA/鈥?2mA
鈥?/div>
Latch-up protection exceeds 500mA per Jedec Std 17
鈥?/div>
ESD protection exceeds 2000 V per MIL STD 883 Method 3015
and 200 V per Machine Model
鈥?/div>
Power-up 3-State
鈥?/div>
Power-up Reset
QUICK REFERENCE DATA
SYMBOL
t
PLH
t
PHL
C
IN
C
OUT
I
CCZ
PARAMETER
Propagation delay
CP to Qn
Input capacitance
Output capacitance
Total supply current
CONDITIONS
T
amb
= 25擄C; GND = 0V
C
L
= 50pF; V
CC
= 5V
V
I
= 0V or V
CC
Outputs disabled;
V
O
= 0V or V
CC
Outputs disabled; V
CC
=5.5V
TYPICAL
4.4
4
7
500
UNIT
ns
pF
pF
nA
ORDERING INFORMATION
PACKAGES
24-Pin Plastic DIP
24-Pin plastic SO
24-Pin Plastic SSOP Type II
24-Pin Plastic TSSOP Type I
TEMPERATURE RANGE
鈥?0擄C to +85擄C
鈥?0擄C to +85擄C
鈥?0擄C to +85擄C
鈥?0擄C to +85擄C
OUTSIDE NORTH AMERICA
74ABT823 N
74ABT823 D
74ABT823 DB
74ABT823 PW
NORTH AMERICA
74ABT823 N
74ABT823 D
74ABT823 DB
74ABT823PW DH
DWG NUMBER
SOT222-1
SOT137-1
SOT340-1
SOT355-1
PIN CONFIGURATION
PIN DESCRIPTION
PIN NUMBER
SYMBOL
OE
D0-D8
Q0-Q8
CP
CE
MR
GND
V
CC
FUNCTION
Output enable input
(active-Low)
Data inputs
Data outputs
Clock pulse input (active
rising edge)
Clock enable input
(active-Low)
Master reset input
(active-Low)
Ground (0V)
Positive supply voltage
OE
D0
D1
D2
D3
D4
D5
D6
D7
1
2
3
4
5
6
7
8
9
24
23
22
21
20
19
18
17
16
15
14
13
TOP VIEW
V
CC
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
CE
CP
1
2, 3, 4, 5, 6,
7, 8, 9, 10
23, 22, 21, 20,
19,18, 17, 16, 15
13
14
11
12
24
D8 10
MR 11
GND 12
SA00227
1995 Sep 06
1
853鈥?617 15703

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