單片機(jī)的英文簡(jiǎn)單介紹...誰(shuí)知道哪有中文版的 麻煩貼下 或者發(fā)到我郵箱了wawy3344@163.com

謝謝謝謝

1
Features
• High-performance, Low-POWER AVR® 8-bit Microcontroller
• ADVANCED RISC Architecture
– 131 Powerful Instructions – Most Single-clock Cycle Execution
– 32 x 8 General Purpose Working Registers
– Fully Static Operation
– Up to 16 MIPS Throughput at 16 MHz
– On-chip 2-cycle Multiplier
• Nonvolatile Program and Data Memories
– 16K Bytes of In-System Self-Programmable FLASH.html">FLASH
Endurance: 10,000 Write/Erase Cycles
– Optional Boot Code Section with Independent LOCK Bits
In-System PROGRAMMING.html">PROGRAMMING by On-chip Boot Program
True Read-While-Write Operation
– 512 Bytes EEPROM
Endurance: 100,000 Write/Erase Cycles
– 1K Byte Internal SRAM
– PROGRAMMING.html">PROGRAMMING LOCK for SOFTWARE Security
• JTAG (IEEE std. 1149.1 Compliant) Interface
– Boundary-scan Capabilities According to the JTAG STANDARD
– Extensive On-chip Debug SUPPORT
– PROGRAMMING.html">PROGRAMMING of FLASH.html">FLASH, EEPROM, Fuses, and LOCK Bits through the JTAG Interface
• Peripheral Features
– Two 8-bit Timer/Counters with Separate Prescalers and Compare Modes
– One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture
Mode
– Real Time Counter with Separate Oscillator
– Four PWM Channels
– 8-channel, 10-bit ADC
8 Single-ended Channels
7 Differential Channels in TQFP PACKAGE ONLY
2 Differential Channels with Programmable Gain at 1x, 10x, or 200X
– Byte-oriented Two-wire Serial Interface
– Programmable Serial USART
– Master/Slave SPI Serial Interface
– Programmable Watchdog Timer with Separate On-chip Oscillator
– On-chip ANALOG Comparator
• Special Microcontroller Features
– Power-on Reset and Programmable Brown-out Detection
– Internal Calibrated RC Oscillator
– External and Internal Interrupt Sources
– Six Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, Standby
and Extended Standby
• I/O and PACKAGEs
– 32 Programmable I/O Lines
– 40-pin PDIP, 44-lead TQFP, and 44-pad MLF
• Operating Voltages
– 2.7 - 5.5V for ATMEGA16L
– 4.5 - 5.5V for ATMEGA16
• Speed Grades
– 0 - 8 MHz for ATMEGA16L
– 0 - 16 MHz for ATMEGA16
8-bit
Microcontroller
with 16K Bytes
In-System
Programmable
FLASH.html">FLASH
ATMEGA16
ATMEGA16L
Preliminary
Rev. 2466E–AVR–10/02
2 ATMEGA16(L)
2466E–AVR–10/02
Pin Configurations Figure 1. Pinouts ATMEGA16
Disclaimer Typical values contained in this data sheet are based on simulations and characterization
of other AVR microcontrollers manufactured on the same PROCESS TECHNOLOGY. Min
and Max values will be available after the DEVICE is characterized.
(XCK/T0) PB0
(T1) PB1
(INT2/AIN0) PB2
(OC0/AIN1) PB3
(SS) PB4
(MOSI) PB5
(MISO) PB6
(SCK) PB7
RESET
VCC
GND
XTAL2
XTAL1
(RXD) PD0
(TXD) PD1
(INT0) PD2
(INT1) PD3
(OC1B) PD4
(OC1A) PD5
(ICP) PD6
PA0 (ADC0)
PA1 (ADC1)
PA2 (ADC2)
PA3 (ADC3)
PA4 (ADC4)
PA5 (ADC5)
PA6 (ADC6)
PA7 (ADC7)
AREF
GND
AVCC
PC7 (TOSC2)
PC6 (TOSC1)
PC5 (TDI)
PC4 (TDO)
PC3 (TMS)
PC2 (TCK)
PC1 (SDA)
PC0 (SCL)
PD7 (OC2)
PA4 (ADC4)
PA5 (ADC5)
PA6 (ADC6)
PA7 (ADC7)
AREF
GND
AVCC
PC7 (TOSC2)
PC6 (TOSC1)
PC5 (TDI)
PC4 (TDO)
(MOSI) PB5
(MISO) PB6
(SCK) PB7
RESET
VCC
GND
XTAL2
XTAL1
(RXD) PD0
(TXD) PD1
(INT0) PD2
(INT1) PD3
(OC1B) PD4
(OC1A) PD5
(ICP) PD6
(OC2) PD7
VCC
GND
(SCL) PC0
(SDA) PC1
(TCK) PC2
(TMS) PC3
PB4 (SS)
PB3 (AIN1/OC0)
PB2 (AIN0/INT2)
PB1 (T1)
PB0 (XCK/T0)
GND
VCC
PA0 (ADC0)
PA1 (ADC1)
PA2 (ADC2)
PA3 (ADC3)
PDIP
TQFP/MLF
3
ATMEGA16(L)
2466E–AVR–10/02
Overview The ATMEGA16 is a low-POWER CMOS 8-bit microcontroller based on the AVR enhanced
RISC architecture. By executing POWERful instructions in a SINGLE clock cycle, the
ATMEGA16 achieves throughputs approaching 1 MIPS per MHz allowing the SYSTEM
designer to optimize POWER consumption versus PROCESSing speed.
Block Diagram Figure 2. Block Diagram
INTERNAL
OSCILLATOR
OSCILLATOR
WATCHDOG
TIMER
MCU CTRL.
& TIMING
OSCILLATOR
TIMERS/
COUNTERS
INTERRUPT
UNIT
STACK
POINTER
EEPROM
SRAM
STATUS
REGISTER
USART
PROGRAM
COUNTER
PROGRAM
FLASH
INSTRUCTION
REGISTER
INSTRUCTION
DECODER
PROGRAMMING
LOGIC SPI
ADC
INTERFACE
COMP.
INTERFACE
PORTA DRIVERS/BUFFERS
PORTA DIGITAL INTERFACE
GENERAL
PURPOSE
REGISTERS
X
Y
Z
ALU
+
-
PORTC DRIVERS/BUFFERS
PORTC DIGITAL INTERFACE
PORTB DIGITAL INTERFACE
PORTB DRIVERS/BUFFERS
PORTD DIGITAL INTERFACE
PORTD DRIVERS/BUFFERS
XTAL1
XTAL2
RESET
CONTROL
LINES
VCC
GND
MUX &
ADC
AREF
PA0 - PA7 PC0 - PC7
PD0 - PD7 PB0 - PB7
AVR CPU
TWI
AVCC
INTERNAL
CALIBRATED
OSCILLATOR
4 ATMEGA16(L)
2466E–AVR–10/02
The AVR core combines a rich instruction set with 32 general purpose working registers.
All the 32 registers are directly connected to the Arithmetic LOGIC Unit (ALU), allowing
two independent registers to be accessed in one SINGLE instruction executed in one clock
cycle. The resulting architecture is more code efficient while achieving throughputs up to
ten times FASTer than conventional CISC microcontrollers.
The ATMEGA16 provides the following features: 16K bytes of In-System Programmable
FLASH.html">FLASH Program MEMORY with Read-While-Write capabilities, 512 bytes EEPROM, 1K
byte SRAM, 32 general purpose I/O lines, 32 general purpose working registers, a
JTAG interface for Boundary-scan, On-chip Debugging SUPPORT and PROGRAMMING, three
flexible Timer/Counters with compare modes, Internal and External Interrupts, a serial
programmable USART, a byte oriented Two-wire Serial Interface, an 8-channel, 10-bit
ADC with optional differential input stage with programmable gain (TQFP PACKAGE ONLY),
a programmable Watchdog Timer with Internal Oscillator, an SPI serial port, and six
SOFTWARE selectable POWER saving modes. The Idle mode stops the CPU while allowing
the USART, Two-wire interface, A/D Converter, SRAM, Timer/Counters, SPI port, and
interrupt SYSTEM to continue functioning. The Power-down mode saves the register contents
but freezes the Oscillator, disabling all other chip functions until the next External
Interrupt or HARDWARE Reset. In Power-save mode, the Asynchronous Timer continues
to run, allowing the user to maintain a timer base while the rest of the DEVICE is sleeping.
The ADC Noise Reduction mode stops the CPU and all I/O MODULES except Asynchronous
Timer and ADC, to minimize switching noise during ADC conversions. In Standby
mode, the crystal/resonator Oscillator is running while the rest of the DEVICE is sleeping.
This allows very FAST start-up combined with low-POWER consumption. In Extended
Standby mode, both the main Oscillator and the Asynchronous Timer continue to run.
The DEVICE is manufactured using ATMEL’s high density nonvolatile MEMORY TECHNOLOGY.
The On-chip ISP FLASH.html">FLASH allows the program MEMORY to be reprogrammed in-SYSTEM
through an SPI serial interface, by a conventional nonvolatile MEMORY programmer, or
by an On-chip Boot program running on the AVR core. The boot program can use any
interface to download the application program in the Application FLASH.html">FLASH MEMORY. SOFTWARE
in the Boot FLASH.html">FLASH section will continue to run while the Application FLASH.html">FLASH section is
updated, providing true Read-While-Write operation. By combining an 8-bit RISC CPU
with In-Sys