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K4H560438D-GCB0 Datasheet

  • K4H560438D-GCB0

  • DDR 256Mb

  • 26頁(yè)

  • SAMSUNG   SAMSUNG

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K4H561638D
B3
(DDR333)
Min
Mode register set cycle time
DQ & DM setup time to DQS
DQ & DM hold time to DQS
Control & Address input pulse width
DQ & DM input pulse width
Power down exit time
Exit self refresh to non-Read command
Exit self refresh to read command
Refresh interval time
Output DQS valid window
Clock half period
Data hold skew factor
DQS write postamble time
Active to Read with Auto precharge
command
Autoprecharge write recovery +
Precharge time
tMRD
tDS
tDH
tIPW
tDIPW
tPDEX
tXSNR
tXSRD
tREFI
tQH
tHP
tQHS
tWPST
tRAP
0.4
18
(tWR/tCK)
+
(tRP/tCK)
12
0.45
0.45
2.2
1.75
6
75
200
7.8
tHP
-tQHS
tCLmin
or tCHmin
-
-
0.5
0.6
0.4
20
(tWR/tCK)
+
(tRP/tCK)
DDR SDRAM
A2
(DDR266A)
Min
15
0.5
0.5
2.2
1.75
7.5
75
200
7.8
tHP
-tQHS
tCLmin
or tCHmin
-
-
0.75
0.6
0.4
20
(tWR/tCK)
+
(tRP/tCK)
Parameter
Symbol
B0
(DDR266B)
Min
15
0.5
0.5
2.2
1.75
7.5
75
200
7.8
tHP
-tQHS
tCLmin
or tCHmin
-
-
0.75
0.6
Unit
ns
ns
ns
ns
ns
ns
ns
tCK
us
ns
ns
ns
tCK
Note
Max
Max
Max
7,8,9
7,8,9
4
1
5
3
tDAL
tCK
11
1. Maximum burst refresh cycle : 8
2. The specific requirement is that DQS be valid(High or Low) on or before this CK edge. The case shown(DQS going from
High_Z to logic Low) applies when no writes were previously in progress on the bus. If a previous write was in progress,
DQS could be High at this time, depending on tDQSS.
3. The maximum limit for this parameter is not a device limit. The device will operate with a great value for this parameter,
but system performance (bus turnaround) will degrade accordingly.
4. A write command can be applied with t
RCD
satisfied after this command.
5. For registered DIMMs, t
CL
and t
CH
are
鈮?/div>
45% of the period including both the half period jitter (t
JIT(HP)
) of the PLL and the half period
jitter due to crosstalk (t
JIT
(crosstalk)
) on the DIMM.
6. Input Setup/Hold Slew Rate Derating
Input Setup/Hold Slew Rate
(V/ns)
0.5
0.4
0.3
鈭唗IS
(ps)
0
+50
+100
鈭唗IH
(ps)
0
+50
+100
This derating table is used to increase t
IS
/t
IH
in the case where the input slew rate is below 0.5V/ns. Input setup/hold slew rate
based on the lesser of AC-AC slew rate and DC-DC slew rate.
7. I/O Setup/Hold Slew Rate Derating
I/O Setup/Hold Slew Rate
(V/ns)
0.5
0.4
0.3
鈭唗DS
(ps)
0
+75
+150
鈭唗DH
(ps)
0
+75
+150
This derating table is used to increase t
DS
/t
DH
in the case where the I/O slew rate is below 0.5V/ns. I/O setup/hold slew rate
based on the lesser of AC-AC slew rate and DC-DC slew rate.
- 24 -
Rev. 2.2 Mar. 鈥?3

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