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K4H56038D-TC Datasheet

  • K4H56038D-TC

  • 256Mb D-die DDR400 SDRAM Specification

  • 18頁

  • SAMSUNG   SAMSUNG

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DDR SDRAM 256Mb D-die (x8, x16)
Key Features
鈥?200MHz Clock, 400Mbps data rate.
鈥?VDD= +2.6V + 0.10V, VDDQ= +2.6V + 0.10V
鈥?Double-data-rate architecture; two data transfers per clock cycle
鈥?Bidirectional data strobe(DQS)
鈥?Four banks operation
鈥?Differential clock inputs(CK and CK)
鈥?DLL aligns DQ and DQS transition with CK transition
鈥?MRS cycle with address key programs
-. Read latency 3 (clock) for DDR400 , 2.5 (clock) for DDR333
-. Burst length (2, 4, 8)
-. Burst type (sequential & interleave)
鈥?All inputs except data & DM are sampled at the positive going edge of the system clock(CK)
鈥?Data I/O transactions on both edges of data strobe
鈥?Edge aligned data output, center aligned data input
鈥?LDM,UDM for write masking only (x16)
鈥?DM for write masking only (x8)
鈥?Auto & Self refresh
鈥?7.8us refresh interval(8K/64ms refresh)
鈥?Maximum burst refresh cycle : 8
DDR SDRAM
鈥?66pin TSOP II package
Ordering Information
Part No.
K4H560838D-TCCC
K4H560838D-TCC4
K4H561638D-TCCC
K4H561638D-TCC4
16M x 16
32M x 8
Org.
Max Freq.
CC(DDR400@CL=3)
C4(DDR400@CL=3)
CC(DDR400@CL=3)
C4(DDR400@CL=3)
SSTL2
66pin TSOP II
Interface
SSTL2
Package
66pin TSOP II
Operating Frequencies
- CC(DDR400@CL=3)
Speed @CL3
CL-tRCD-tRP
*CL : CAS Latency
200MHz
3-3-3
- C4(DDR400@CL=3)
200MHz
3-4-4
Rev. 1.1 Feb. 2003

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