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K4H56038D-TC Datasheet

  • K4H56038D-TC

  • 256Mb D-die DDR400 SDRAM Specification

  • 169.81KB

  • 18頁

  • SAMSUNG   SAMSUNG

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DDR SDRAM 256Mb D-die (x8, x16)
DDR SDRAM I
DD
spec table
Symbol
IDD0
IDD1
IDD2P
IDD2F
IDD2Q
IDD3P
IDD3N
IDD4R
IDD4W
IDD5
IDD6
Normal
Low power
IDD7A
32Mx8
105
130
4
30
25
55
75
185
220
200
3
1.5
350
100
130
4
30
25
55
75
185
220
200
3
1.5
350
110
150
4
30
25
55
75
220
250
200
3
1.5
380
16Mx16
105
145
4
30
25
55
75
220
250
200
3
1.5
380
DDR SDRAM
(V
DD
=2.7V, T = 10擄C)
- CC(DDR400@CL=3) - C4(DDR400@CL=3) - CC(DDR400@CL=3) - C4(DDR400@CL=3)
Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
Notes
mA Optional
mA
< Detailed test conditions for DDR SDRAM IDD1 & IDD7A >
IDD1 : Operating current: One bank operation
1. Only one bank is accessed with tRC(min), Burst Mode, Address and Control inputs change logic state once per Deselect cycle.
Iout = 0mA
2. Timing patterns
- CC/C4(200Mhz,CL=3) : tCK=5ns, CL=3, BL=4, tRCD=3*tCK(CC) 4*tCK(C4), tRC=11*tCK(CC) 12*tCK(C4), tRAS=8*tCK
Setup : A0 N N R0 N N N N P0 N N
Read : A0 N N R0 N N N N P0 N N - repeat the same timing with random address changing
*50% of data changing at every transfer
IDD7A : Operating current: Four bank operation
1. Four banks are being interleaved with tRC(min), Burst Mode, Address and Control inputs on Deselet edge are not changing.
Iout = 1mA
2. Timing patterns
- CC/C4(200Mhz,CL=3) : tCK=5ns, CL=3, BL=4, tRCD=3*tCK(CC) 4*tCK(C4), tRC=11*tCK(CC) 12*tCK(C4), tRAS=8*tCK
Setup : A0 N A1 RA0 A2 RA1 A3 RA2 N RA3 N N
Read : A0 N A1 RA0 A2 RA1 A3 RA2 N RA3 N N - repeat the same timing with random address changing
*50% of data changing at every transfer
Legend : A = Activate, R=Read, W=Write, P=Precharge, N=NOP
Rev. 1.1 Feb. 2003

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