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K4H510838B-VC/LB0 Datasheet

  • K4H510838B-VC/LB0

  • 512Mb B-die DDR SDRAM Specification 54 sTSOP-II (400mil x 44...

  • 24頁(yè)

  • SAMSUNG   SAMSUNG

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DDR SDRAM 512Mb B-die (x8)
8.0 Command Truth Table
COMMAND
Register
Register
Extended MRS
Mode Register Set
Auto Refresh
Refresh
Self
Refresh
Entry
Exit
CKEn-1 CKEn
H
H
H
L
H
H
H
H
Bank Selection
All Banks
Entry
Exit
Entry
Precharge Power Down Mode
Exit
DM(UDM/LDM for x16 only)
No operation (NOP) : Not defined
L
H
H
X
H
L
H
H
H
L
H
X
X
H
L
H
X
X
X
X
X
L
H
L
CS
L
L
L
L
H
L
L
L
L
L
H
L
X
H
L
H
L
RAS
L
L
L
H
X
L
H
H
H
L
X
V
X
X
H
X
V
X
X
H
X
H
X
H
CAS
L
L
L
H
X
H
L
L
H
H
X
V
X
X
H
X
V
WE
L
L
H
H
X
H
H
L
L
L
X
V
X
X
H
X
V
V
X
L
H
V
V
V
L
H
L
H
DDR SDRAM
(V=Valid, X=Don鈥瞭 Care, H=Logic High, L=Logic Low)
BA0,1 A10/AP
A0 ~ A9,
A11 ~ A12
Note
1, 2
1, 2
3
3
3
3
4
4
4
4, 6
7
X
5
OP CODE
OP CODE
X
X
Row Address
Column
Address
Column
Address
Bank Active & Row Addr.
Read &
Column Address
Write &
Column Address
Burst Stop
Precharge
Auto Precharge Disable
Auto Precharge Enable
Auto Precharge Disable
Auto Precharge Enable
X
Active Power Down
X
X
X
X
8
9
9
Note :
1. OP Code : Operand Code. A
0
~ A
13
& BA
0
~ BA
1
: Program keys. (@EMRS/MRS)
2. EMRS/MRS can be issued only at all banks precharge state.
A new command can be issued 2 clock cycles after EMRS or MRS.
3. Auto refresh functions are same as the CBR refresh of DRAM.
The automatical precharge without row precharge command is meant by "Auto".
Auto/self refresh can be issued only at all banks precharge state.
4. BA
0
~ BA
1
: Bank select addresses.
If both BA
0
and BA
1
are "Low" at read, write, row active and precharge, bank A is selected.
If BA
0
is "High" and BA
1
is "Low" at read, write, row active and precharge, bank B is selected.
If BA
0
is "Low" and BA
1
is "High" at read, write, row active and precharge, bank C is selected.
If both BA
0
and BA
1
are "High" at read, write, row active and precharge, bank D is selected.
5. If A
10
/AP is "High" at row precharge, BA
0
and BA
1
are ignored and all banks are selected.
6. During burst write with auto precharge, new read/write command can not be issued.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at t
RP
after the end of burst.
7. Burst stop command is valid at every burst length.
8. DM(x4/8) sampled at the rising and falling edges of the DQS and Data-in are masked at the both edges (Write DM latency is 0).
UDM/LDM(x16 only) sampled at the rising and falling edges of the UDQS/LDQS and Data-in are masked at the both edges
(Write UDM/LDM latency is 0).
9. This combination is not defined for any function, which means "No Operation(NOP)" in DDR SDRAM.
Rev. 1.3 June. 2005

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