DDR SDRAM 512Mb B-die (x8)
4.0 Pin Description
DDR SDRAM
64Mb x 8
VDD
DQ0
VDDQ
DQ1
VSSQ
DQ2
VDDQ
DQ3
VSSQ
NC
VDDQ
NC
NC
VDD
WE
CAS
RAS
CS
NC
BA0
BA1
AP/A10
A0
A1
A2
A3
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
VSS
DQ7
VSSQ
DQ6
VDDQ
DQ5
VSSQ
DQ4
VDDQ
NC
VSSQ
DQS
VREF
VSS
DM
CK
CK
CKE
A12
A11
A9
A8
A7
A6
A5
A4
VSS
54 Pin sTSOP(II)
400mil x 441mil
(0.4 mm Pin Pitch)
Bank Address
BA0-BA1
Row Address
A0-A12
Auto Precharge
A10
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
512Mb sTSOP(II)-400 Package Pinout
Organization
64Mx8
Row Address
A0~A12
Column Address
A0-A9, A11
DM is internally loaded to match DQ and DQS identically.
Row & Column address configuration
Rev. 1.3 June. 2005