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DDR SDRAM 512Mb B-die (x8)

1.0 Key Features

鈥?VDD : 2.5V 鹵 0.2V, VDDQ : 2.5V 鹵 0.2V for DDR266, 333

鈥?VDD : 2.6V 鹵 0.1V, VDDQ : 2.6V 鹵 0.1V for DDR400

鈥?Double-data-rate architecture; two data transfers per clock cycle

鈥?Bidirectional data strobe [DQS] (x4,x8)

鈥?Four banks operation

鈥?Differential clock inputs(CK and CK)

鈥?DLL aligns DQ and DQS transition with CK transition

鈥?MRS cycle with address key programs

-. Read latency : DDR266(2, 2.5 Clock), DDR333(2.5 Clock), DDR400(3 Clock)

-. Burst length (2, 4, 8)

-. Burst type (sequential & interleave)

鈥?All inputs except data & DM are sampled at the positive going edge of the system clock(CK)

鈥?Data I/O transactions on both edges of data strobe

鈥?Edge aligned data output, center aligned data input

鈥?DM for write masking only (x4, x8)

鈥?Auto & Self refresh

鈥?7.8us refresh interval(8K/64ms refresh)

鈥?Maximum burst refresh cycle : 8

鈥?54pin sTSOP(II)-400

(Leaded & Pb-Free(RoHS compliant))

package

DDR SDRAM

2.0 Ordering Information

Part No.

K4H510838B-N(V)C/LCC

K4H510838B-N(V)C/LB3

K4H510838B-N(V)C/LA2

K4H510838B-N(V)C/LB0

64M x 8

Org.

Max Freq.

CC(DDR400@CL=3)

B3(DDR333@CL=2.5)

A2(DDR266@CL=2)

B0(DDR266@CL=2.5)

SSTL2

54pin sTSOP II

Interface

Package

Note : Leaded and Lead-free(Pb-free) can be discriminated by PKG P/N (N : 54 sTSOP with Leaded, V : 54 sTSOP with Lead-free)

3.0 Operating Frequencies

CC(DDR400@CL=3)

Speed @CL2

Speed @CL2.5

Speed @CL3

CL-tRCD-tRP

-

166MHz

200MHz

3-3-3

B3(DDR333@CL=2.5)

133MHz

166MHz

-

2.5-3-3

A2(DDR266@CL=2.0)

133MHz

133MHz

-

2-3-3

B0(DDR266@CL=2.5)

100MHz

133MHz

-

2.5-3-3

Rev. 1.3 June. 2005

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