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D17133CS Datasheet

  • D17133CS

  • 4-BIT SINGLE-CHIP MICROCONTROLLER

  • 289頁

  • NEC   NEC

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CHAPTER 5
DATA MEMORY (RAM)
Figure 5-4. General Register (GR) Configuration
BANK0
0
0
1
2
3
4
5
6
7
Row address
1
2
3
4
5
Column address
General register
6
7
8
9
A
B
C
D
E
F
Area specifiable as general register
Pointed to by general register
pointer (RP) in system register.
Note that row addresses 4 to 6
in the case of the
碌
PD17120
and 17121 are uninstalled mem-
ory locations. The register
pointer (RP) should therefore
not specify a row address in this
area.
Port register
SYSREG
5.1.4 Port Registers
A port register consists of five nibbles allocated at addresses 6FH to 73H in Bank0 of the data memory. As shown
in Figure 5-5, the two high-order bits of address 6FH are always set to 0.
Figure 5-5 shows the configuration of the port registers.
Figure 5-5. Port Register Configuration
Port Register
Address
6FH
P0E
Symbol
BANK0
0
0
P
0
E
1
P
0
E
0
P
0
A
3
70H
P0A
P
0
A
2
P
0
A
1
P
0
A
0
P
0
B
3
71H
P0B
P
0
B
2
P
0
B
1
P
0
B
0
P
0
C
3
72H
P0C
P
0
C
2
P
0
C
1
P
0
C
0
P
0
D
3
73H
P0D
P
0
D
2
P
0
D
1
P
0
D
0
5.1.5 General Data Memory
General data memory is all the data memory not used by the port and system registers (SYSREG). In other words,
general data memory consists of 64 nibbles (
碌
PD17120 and 17121) or 111 nibbles (
碌
PD17132, 17133, 17P132, and
17P133).
5.1.6 Uninstalled Data Memory
There is no hardware installed at addresses 40H to 6EH of the
碌
PD17120 and 17121. Any attempt to read this
area will yield unpredictable results. Writing data to this area is invalid and should therefore not be attempted.
33

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