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K4D261638E-TC40 Datasheet

  • K4D261638E-TC40

  • 2M x 16Bit x 4 Banks Double Data Rate Synchronous DRAM

  • 16頁

  • SAMSUNG   SAMSUNG

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K4D261638E
AC CHARACTERISTICS
Parameter
CK cycle time
CK high level width
CL=3
CL=4
128M DDR SDRAM
Sym-
bol
-2A
Min
-
2.86
0.45
0.45
-0.6
-0.6
-
0.9
0.4
0.85
0
0.35
0.4
0.4
0.4
0.9
0.9
0.35
0.35
tCLmin
or
tCHmin
tHP-
0.35
-33
Max
10
0.55
0.55
0.6
0.6
0.35
1.1
0.6
1.15
-
-
0.6
0.6
0.6
-
-
-
-
-
-
-36
Max
10
0.55
0.55
0.6
0.6
0.35
1.1
0.6
1.15
-
-
0.6
0.6
0.6
-
-
-
-
-
-
-40
Max
10
0.55
0.55
0.6
0.6
0.40
1.1
0.6
1.15
-
-
0.6
0.6
0.6
-
-
-
-
-
-
-50
Max
10
0.55
0.55
0.6
0.6
0.4
1.1
0.6
1.15
-
-
0.6
0.6
0.6
-
-
-
-
-
-
Min
-
3.3
0.45
0.45
-0.6
-0.6
-
0.9
0.4
0.85
0
0.35
0.4
0.4
0.4
0.9
0.9
0.35
0.35
tCLmin
or
tCHmin
tHP-
0.35
Min
-
3.6
0.45
0.45
-0.6
-0.6
-
0.9
0.4
0.85
0
0.35
0.4
0.4
0.4
0.9
0.9
0.40
0.40
tCLmin
or
tCHmin
tHP-0.4
Min
4.0
-
0.45
0.45
-0.6
-0.6
-
0.9
0.4
0.85
0
0.35
0.4
0.4
0.4
0.9
0.9
0.4
0.4
tCLmin
or
tCHmin
tHP-0.4
Min
5.0
-
0.45
0.45
-0.7
-0.7
-
0.9
0.4
0.8
0
0.3
0.4
0.4
0.4
1.0
1.0
0.45
0.45
tCLmin
or
tCHmin
tHP-
0.45
Max
10
0.55
0.55
0.7
0.7
0.45
1.1
0.6
1.2
-
-
0.6
0.6
0.6
-
-
-
-
-
-
Unit Note
ns
ns
tCK
tCK
ns
ns
ns
tCK
tCK
tCK
ns
tCK
tCK
tCK
tCK
ns
ns
ns
ns
ns
ns
1
1
1
t
CK
t
CH
CK low level width
t
CL
DQS out access time from CK
t
DQSCK
Output access time from CK
t
AC
Data strobe edge to Dout edge
t
DQSQ
Read preamble
t
RPRE
Read postamble
t
RPST
CK to valid DQS-in
t
DQSS
DQS-In setup time
t
WPRES
DQS-in hold time
t
WPREH
DQS write postamble
t
WPST
DQS-In high level width
t
DQSH
DQS-In low level width
t
DQSL
Address and Control input setup
t
IS
Address and Control input hold
t
IH
DQ and DM setup time to DQS
t
DS
DQ and DM hold time to DQS
t
DH
Clock half period
Data output hold time from DQS
t
HP
t
QH
Note 1 :
- The JEDEC DDR specification currently defines the output data valid window(tDV) as the time period when the data
strobe and all data associated with that data strobe are coincidentally valid.
- The previously used definition of tDV(=0.35tCK) artificially penalizes system timing budgets by assuming the worst
case
output vaild window even then the clock duty cycle applied to the device is better than 45/55%
- A new AC timing term, tQH which stands for data output hold time from DQS is difined to account for clock duty cycle
variation and replaces tDV
- tQHmin = tHP-X where
. tHP=Minimum half clock period for any given cycle and is defined by clock high or clock low time(tCH,tCL)
. X=A frequency dependent timing allowance account for tDQSQmax
- 13 -
Rev. 1.2 (Jul. 2003)

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