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K4D553238F Datasheet

  • K4D553238F

  • 256Mbit GDDR SDRAM

  • 17頁

  • SAMSUNG   SAMSUNG

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K4D553238F-GC
256M GDDR SDRAM
2M x 32Bit x 4 Banks Graphic Double Data Rate Synchronous DRAM
with Bi-directional Data Strobe and DLL
FEATURES
鈥?2.5V 鹵 5% power supply for device operation
鈥?2.5V 鹵 5% power supply for I/O interface
鈥?SSTL_2 compatible inputs/outputs
鈥?4 banks operation
鈥?MRS cycle with address key programs
-. Read latency 4, 5 and 6 (clock)
-. Burst length (2, 4 and 8)
-. Burst type (sequential & interleave)
鈥?All inputs except data & DM are sampled at the positive
going edge of the system clock
鈥?Differential clock input
鈥?No Wrtie-Interrupted by Read Function
鈥?4 DQS鈥檚 ( 1DQS / Byte )
鈥?Data I/O transactions on both edges of Data strobe
鈥?DLL aligns DQ and DQS transitions with Clock transition
鈥?Edge aligned data & data strobe output
鈥?Center aligned data & data strobe input
鈥?DM for write masking only
鈥?Auto & Self refresh
鈥?32ms refresh period (4K cycle)
鈥?144-Ball FBGA
鈥?Maximum clock frequency up to 350MHz
鈥?Maximum data rate up to 700Mbps/pin
ORDERING INFORMATION
Part NO.
K4D553238F-GC2A
K4D553238F-GC33
K4D553238F-GC36
Max Freq.
350MHz
300MHz
275MHz
Max Data Rate
700Mbps/pin
600Mbps/pin
550Mbps/pin
SSTL_2
144-Ball FBGA
Interface
Package
* K4D553238F-VC is the Lead Free package part number.
GENERAL DESCRIPTION
FOR 2M x 32Bit x 4 Bank DDR SDRAM
The K4D553238F is 268,435,456 bits of hyper synchronous data rate Dynamic RAM organized as 4 x 2,097,152 words by
32 bits, fabricated with SAMSUNG
鈥?/div>
s high performance CMOS technology. Synchronous features with Data Strobe allow
extremely high performance up to 2.8GB/s/chip. I/O transactions are possible on both edges of the clock cycle. Range of
operating frequencies, programmable burst length and programmable latencies allow the device to be useful for a variety
of high performance memory system applications.
- 3 -
Rev 1.3 (Mar. 2005)

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