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K4D263238G-VC Datasheet

  • K4D263238G-VC

  • 128Mbit GDDR SDRAM

  • 20頁

  • SAMSUNG   SAMSUNG

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K4D263238G-GC
MODE REGISTER SET(MRS)
128M GDDR SDRAM
The mode register stores the data for controlling the various operating modes of DDR SDRAM. It programs CAS latency,
addressing mode, burst length, test mode, DLL reset and various vendor specific options to make DDR SDRAM useful for
variety of different applications. The default value of the mode register is not defined, therefore the mode register must be
written after EMRS setting for proper operation. The mode register is written by asserting low on CS, RAS, CAS and
WE(The DDR SDRAM should be in active mode with CKE already high prior to writing into the mode register). The state of
address pins A
0
~ A
11
and BA
0
, BA
1
in the same cycle as CS, RAS, CAS and WE going low is written in the mode register.
Minimum two clock cycles are requested to complete the write operation in the mode register. The mode register contents
can be changed using the same command and clock cycle requirements during operation as long as all banks are in the
idle state. The mode register is divided into various fields depending on functionality. The burst length uses A
0
~ A
2
,
addressing mode uses A
3
, CAS latency(read latency from column address) uses A
4
~ A
6
. A
7
is used for test mode. A
8
is
used for DLL reset. A
7,
A
8
, BA
0
and BA
1
must be set to low for normal MRS operation. Refer to the table for specific codes
for various burst length, addressing modes and CAS latencies.
BA
1
RFU
BA
0
0
A
11
A
10
RFU
A
9
A
8
DLL
A
7
TM
A
6
A
5
A
4
A
3
BT
A
2
A
1
A
0
Address Bus
Mode Register
CAS Latency
Burst Length
DLL
A
8
0
1
DLL Reset
No
Yes
Test Mode
A
7
0
1
mode
Normal
Test
Burst Type
A
3
0
1
Type
Sequential
Interleave
Burst Length
0
CAS Latency
BA
0
0
1
A
n
~ A
0
MRS
EMRS
A
6
0
0
0
* RFU(Reserved for future use)
should stay "0" during MRS
cycle.
0
1
1
1
1
MRS Cycle
0
CK, CK
Command
NOP
Precharge
All Banks
NOP
NOP
MRS
A
5
0
0
1
1
0
0
1
1
A
4
0
1
0
1
0
1
0
1
Latency
Reserved
Reserved
Reserved
3
4
Reserved
Reserved
Reserved
A
2
0
0
0
0
1
1
1
1
A
1
0
0
1
1
0
0
1
1
A
0
0
1
0
1
0
1
0
1
Burst Type
Sequential
Reserve
2
4
8
Reserve
Reserve
Reserve
Full page
Interleave
Reserve
2
4
8
Reserve
Reserve
Reserve
Reserve
1
2
3
4
5
6
7
8
NOP
Any
Command
NOP
NOP
t
RP
t
MRD
=2 t
CK
*1 : MRS can be issued only at all banks precharge state.
*2 : Minimum
t
RP
is required to issue MRS command.
- 9 -
Rev 1.8 (March. 2005)

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