K4D263238G-GC
Simplified Timing @ BL=2, CL=4
tCH
tCL
tCK
128M GDDR SDRAM
0
CK, CK
1
2
3
4
5
6
7
8
CS
tDQSCK
tIS
tIH
tDQSS
tDQSH
tDQSL
DQS
tRPRE
tRPST
t
WPREH
t
WPRES
tDS tDH
tDQSQ
tAC
DQ
DM
COMMAND
READA
Qa1
Qa2
Db0
Db1
WRITEB
Simplified Timing(2) @ BL=4
0
CK, CK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
BA[1:0]
BAa
BAa
BAa
BAa
BAb
BAa
BAb
A8/AP
Ra
Ra
Ca
Ra
Rb
ADDR
(A0~A7,
Ra
A9,A10)
WE
Ra
Rb
Ca
Cb
DQS
DQ
Da0 Da1 Da2 Da3
Da0 Da1 Da2 Da3 Db0 Db1 Db2 Db3
DM
COMMAND
ACTIVEA
WRITEA
PRECH
ACTIVEA
ACTIVEB WRITEA
WRITEB
tRCD
tRAS
tRC
tRP
tRRD
Normal Write Burst
(@ BL=4)
Multi Bank Interleaving Write Burst
(@ BL=4)
- 19 -
Rev 1.8 (March. 2005)