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Rx5C348A/B

Address Mapping

Address

A3A2A1A0

0 0 0 0 0

1 0 0 0 1

2 0 0 1 0

3 0 0 1 1

4 0 1 0 0

5 0 1 0 1

6 0 1 1 0

7 0 1 1 1

Register Name

Second Counter

Minute Counter

Hour Counter

Day-of-week Counter

Day-of-month

Counter

Month Counter and

Century Bit

Year Counter

Oscillation

Adjustment

Register *3)

Alarm_W

(Minute Register)

Alarm_W

(Hour Register)

Alarm_W

(Day-of-week

Register)

Alarm_D

(Minute Register)

Alarm_D

(Hour Register)

Control

*3)

Control

*3)

Register

Register

1

2

D7

-

*2)

-

-

-

-

/19鈰?0

Y80

(0)

*4)

-

-

-

D6

S40

M40

-

-

-

-

Y40

F6

D5

S20

M20

H20

P鈰?A

-

D20

-

Y20

F5

Data

D4

D3

S10

S8

M10

H10

-

D10

MO10

Y10

F4

M8

H8

-

D8

MO8

Y8

F3

D2

S4

M4

H4

W4

D4

MO4

Y4

F2

D1

S2

M2

H2

W2

D2

MO2

Y2

F1

D0

S1

M1

H1

W1

D1

MO1

Y1

F0

8 1 0 0 0

9 1 0 0 1

A 1 0 1 0

WM40

-

WW6

WM20

WH20

WP鈰? A

WW5

WM10

WH10

WW4

WM8

WH8

WW3

WM4

WH4

WW2

WM2

WH2

WW1

WM1

WH1

WW0

B 1 0 1 1

C 1 1 0 0

D 1 1 0 1

E 1 1 1 0

F 1 1 1 1

-

-

-

WALE

VDSL

DM40

-

-

DALE

VDET

DM20

DH20

DP鈰?A

-

/12鈰?4

SCRA

TCH1

DM10

DH10

DM8

DH8

DM4

DH4

DM2

DH2

DM1

DH1

-

CT0

DAFG

-

-

-

-

/CLEN2 TEST

CT2

CT1

*5)

XSTP /CLEN1 CTFG WAFG

*5)

Notes:

* 1) All the data listed above accept both reading and writing.

* 2) The data marked with "-" is invalid for writing and reset to 0 for reading.

* 3) When the XSTP bit is set to 1 in Control Register 2, all the bits are reset to 0 in Oscillation Adjustment

Register, Control Register 1 and Control Register 2 excluding the XSTP bit.

* 4) Writing to the Oscillation Adjustment Register requires filling the (0) bit.

* 5) These bit names apply to the Rx5C348A. For the Rx5C348B the bit names are SCRATCH2 and

SCRATCH3.

12345

Rev.2.01

- 11 -

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