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K4M51163LE-YPL Datasheet

  • K4M51163LE-YPL

  • 8M x 16Bit x 4 Banks Mobile SDRAM in 54FBGA

  • 114.10KB

  • 12頁(yè)

  • SAMSUNG   SAMSUNG

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K4M51163LE - Y(P)C/L/F
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
Version
Parameter
Row active to row active delay
RAS to CAS delay
Row precharge time
Row active time
t
RAS
(max)
Row cycle time
Last data in to row precharge
Last data in to Active delay
Last data in to new col. address delay
Last data in to burst stop
Col. address to col. address delay
Number of valid output data
Number of valid output data
Number of valid output data
t
RC
(min)
t
RDL
(min)
t
DAL
(min)
t
CDL
(min)
t
BDL
(min)
t
CCD
(min)
CAS latency=3
CAS latency=2
CAS latency=1
67
100
69
2
tRDL + tRP
1
1
1
2
1
0
84
Symbol
-80
t
RRD
(min)
t
RCD
(min)
t
RP
(min)
t
RAS
(min)
16
19
19
48
-1H
19
19
19
50
-1L
19
24
24
60
Mobile-SDRAM
Unit
ns
ns
ns
ns
us
ns
CLK
-
CLK
CLK
CLK
Note
1
1
1
1
1
2
3
2
2
4
ea
5
NOTES:
1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next
higher integer.
2. Minimum delay is required to complete write.
3. Minimum tRDL=2CLK and tDAL(= tRDL + tRP) is required to complete both of last data write command(tRDL) and precharge command(tRP).
4. All parts allow every cycle column address change.
5. In case of row precharge interrupt, auto precharge and read burst stop.
February 2004

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