K4M51163LE - Y(P)C/L/F
A. MODE REGISTER FIELD TABLE TO PROGRAM MODES
Register Programmed with Normal MRS
Address
Function
BA0 ~ BA1
"0" Setting for Normal
MRS
A12 ~ A10/AP
RFU
*1
A9
*2
W.B.L
A8
A7
A6
A5
A4
Mobile-SDRAM
A3
BT
A2
A1
A0
Test Mode
CAS Latency
Burst Length
Normal MRS Mode
Test Mode
A8
0
0
1
1
A7
0
1
0
1
Type
Mode Register Set
Reserved
Reserved
Reserved
A6
0
0
0
0
1
1
1
1
CAS Latency
A5
0
0
1
1
0
0
1
1
A4
0
1
0
1
0
1
0
1
Latency
Reserved
1
2
3
Reserved
Reserved
0
0
1
Burst
Single Bit
Reserved
Reserved
0
Setting
for Nor-
mal MRS
A3
0
1
Burst Type
Type
Sequential
Interleave
Mode Select
BA1 BA0
Mode
A2
0
0
0
0
1
1
1
1
A1
0
0
1
1
0
0
1
1
Burst Length
A0
0
1
0
1
0
1
0
1
BT=0
1
2
4
8
Reserved
Reserved
Reserved
Full Page
BT=1
1
2
4
8
Reserved
Reserved
Reserved
Reserved
Write Burst Length
A9
Length
Full Page Length x16 : 512Mb(1024)
Register Programmed with Extended MRS
Address
Function
BA1
BA0
A12 ~ A10/AP
A9
RFU
*1
A8
A7
A6
DS
A5
A4
A3
A2
A1
PASR
A0
Mode Select
RFU
*1
EMRS for PASR(Partial Array Self Ref.) & DS(Driver Strength)
Mode Select
BA1
0
0
1
1
BA0
0
1
0
1
Mode
Normal MRS
Reserved
EMRS for Mobile SDRAM
Reserved
Reserved Address
A12~A10/AP
0
A9
0
A8
0
A7
0
A4
0
A3
0
1
1
1
Reserved
A6
0
0
1
1
Driver Strength
A5
0
1
0
1
Driver Strength
Full
1/2
Reserved
Reserved
A2
0
0
0
0
1
1
1
A1
0
0
1
1
0
0
1
A0
0
1
0
1
0
1
0
PASR
Size of Refreshed Array
Full Array
1/2 of Full Array
1/4 of Full Array
Reserved
Reserved
Reserved
Reserved
NOTES:
1. RFU(Reserved for future use) should stay "0" during MRS cycle.
2. If A9 is high during MRS cycle, "Burst Read Single Bit Write" function will be enabled.
February 2004