128Mb DDR SDRAM
3.3.12 Write with Auto Precharge
If A10 is high when write command is issued , the write with auto-precharge function is performed. Any new
command to the same bank should not be issued until the internal precharge is completed. The internal pre-
charge begins after keeping tWR(min).
< Burst Length=4 >
0
CK
CK
Command
DQS
DQ
鈥瞫
Din 0
Din 1 Din 2 Din 3
* Bank can be reactivated at
completion of
t
RP
BANK A
ACTIVE
NOP
WRITE A
Auto Precharge
NOP
NOP
NOP
NOP
NOP
NOP
1
2
3
4
5
6
7
8
t
WR
t
RP
Internal precharge start
Figure 20. Write with auto precharge timing
Burst length = 4
Asserted
command
WRITE
WRITE+
AP
READ
READ+AP
Active
Precharge
*1
*2
For same Bank
3
WRITE+
No AP
*1
WRITE+
AP
Illegal
Illegal
Illegal
Illegal
4
WRITE+
No AP
WRITE+
AP
READ+NO
AP+DM
*2
READ +
AP+DM
Illegal
Illegal
5
WRITE+
No AP
WRITE+
AP
READ+NO
AP+DM
READ +
AP+DM
Illegal
Illegal
6
Illegal
Illegal
READ+
NO AP
READ +
AP
Illegal
Illegal
7
Illegal
Illegal
READ+
NO AP
READ +
AP
Illegal
Illegal
8
Illegal
Illegal
Illegal
Illegal
Illegal
Illegal
3
Legal
Legal
Illegal
Illegal
Legal
Legal
For Different Bank
4
Legal
Legal
Illegal
Illegal
Legal
Legal
5
Legal
Legal
Legal
Legal
Legal
Legal
6
Legal
Legal
Legal
Legal
Legal
Legal
7
Legal
Legal
Legal
Legal
Legal
Legal
: AP = Auto Precharge
: DM : Refer to "
3.3.7 Write Interrupted by a Read & DM "
in page 25.
Table 7. Operating description when new command asserted
while write with auto precharge is issued
- 30 -
REV. 1.0 November. 2. 2000