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K4H563238M-TCA0 Datasheet

  • K4H563238M-TCA0

  • 128Mb DDR SDRAM

  • 53頁(yè)

  • SAMSUNG   SAMSUNG

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128Mb DDR SDRAM
8Mx16
Symbol
IDD0
IDD1
IDD2P
IDD2F
IDD2Q
IDD3P
IDD3N
IDD4R
IDD4W
IDD5
IDD6
Normal
Low power
IDD7
K4H281638B-TCA2
(DDR266A)
typical
90
140
21
40
30
25
45
210
150
195
2
1
300
worst
95
155
25
45
35
30
50
245
165
210
2
1
340
K4H281638B-TCB0
(DDR266B)
typical
90
140
21
40
30
25
45
210
150
195
2
1
300
worst
95
155
25
45
35
30
50
245
165
210
2
1
340
K4H281638B-TCA0
(DDR200)
typical
80
135
20
35
27
20
35
155
110
180
2
1
275
worst
85
150
24
40
32
25
40
175
125
190
2
1
300
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
Optional
Unit
Notes
Table 12. 128Mb DDR SDRAM IDD SPEC Table
< Detailed test conditions for DDR SDRAM IDD1 & IDD7 >
IDD1 : Operating current: One bank operation
1. Typical Case : Vdd = 2.5V, T=25鈥機(jī)
2. Worst Case : Vdd = 2.7V, T= 10鈥機(jī)
3. Only one bank is accessed with tRC(min), Burst Mode, Address and Control inputs on NOP edge are changing once
per clock cycle. lout = 0mA
4. Timing patterns
- DDR200(100Mhz, CL=2) : tCK = 10ns, CL2, BL=4, tRCD = 2*tCK, tRAS = 5*tCK
Read : A0 N R0 N N P0 N A0 N - repeat the same timing with random address changing
*50% of data changing at every burst
- DDR266B(133Mhz, CL=2.5) : tCK = 7.5ns, CL=2.5, BL=4, tRCD = 3*tCK, tRC = 9*tCK, tRAS = 5*tCK
Read : A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address changing
*50% of data changing at every burst
- DDR266A (133Mhz, CL=2) : tCK = 7.5ns, CL=2, BL=4, tRCD = 3*tCK, tRC = 9*tCK, tRAS = 5*tCK
Read : A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address changing
*50% of data changing at every burst
Legend : A=Activate, R=Read, W=Write, P=Precharge, N=NOP
- 42 -
REV. 1.0 November. 2. 2000

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