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K4H283238M-TCA0 Datasheet

  • K4H283238M-TCA0

  • 128Mb DDR SDRAM

  • 669.26KB

  • 53頁(yè)

  • SAMSUNG   SAMSUNG

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128Mb DDR SDRAM
3.2.2 Mode Register Definition
3.2.2.1 Mode Register Set(MRS)
The mode register stores the data for controlling the various operating modes of DDR SDRAM. It programs
CAS latency, addressing mode, burst length, test mode, DLL reset and various vendor specific options to make
DDR SDRAM useful for variety of different applications. The default value of the mode register is not defined,
therefore the mode register must be written after EMRS setting for proper DDR SDRAM operation. The mode
register is written by asserting low on CS, RAS, CAS, WE and BA0(The DDR SDRAM should be in all bank pre-
charge with CKE already high prior to writing into the mode register). The states of address pins A0 ~ A11 in
the same cycle as CS, RAS, CAS, WE and BA0 going low are written in the mode register. Two clock cycles
are requested to complete the write operation in the mode register. The mode register contents can be
changed using the same command and clock cycle requirements during operation as long as all banks are in
the idle state. The mode register is divided into various fields depending on functionality. The burst length uses
A0 ~ A2, addressing mode uses A3, CAS latency(read latency from column address) uses A4 ~ A6. A7 is used
for test mode. A8 is used for DLL reset. A7 must be set to low for normal MRS operation. Refer to the table for
specific codes for various burst lengths, addressing modes and CAS latencies.
BA
1
BA
0
A
11
A
10
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
Address Bus
RFU
0
RFU
DLL
TM
CAS Latency
BT
Burst Length
Mode Register
A
8
0
1
DLL Reset
No
Yes
A
7
0
1
mode
Normal
Test
A
3
0
1
Burst Type
Sequential
Interleave
Burst Length
CAS Latency
A
6
BA
0
0
1
A
n
~ A
0
(Existing)MRS Cycle
Extended Funtions(EMRS)
0
0
0
0
1
* RFU(Reserved for future use)
should stay "0" during MRS
cycle.
1
1
1
A
5
0
0
1
1
0
0
1
1
A
4
0
1
0
1
0
1
0
1
Latency
Reserved
Reserved
2
Reserved
Reserved
Reserved
2.5
Reserved
A
2
0
0
0
0
1
1
1
1
A
1
0
0
1
1
0
0
1
1
A
0
0
1
0
1
0
1
0
1
Latency
Sequential
Reserve
2
4
8
Reserve
Reserve
Reserve
Reserve
Interleave
Reserve
2
4
8
Reserve
Reserve
Reserve
Reserve
Figure 5. Mode Register Set
- 15 -
REV. 1.0 November. 2. 2000

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