128Mb DDR SDRAM
Current State
PRECHARG-
ING
(DURING tRP)
CS
L
L
L
L
L
L
RAS CAS
H
H
L
L
L
L
H
H
L
L
L
L
H
H
H
L
L
L
L
H
L
H
H
L
L
H
L
H
H
L
L
H
L
L
H
H
L
L
WE
L
X
H
L
H
L
L
X
H
L
H
L
L
H
L
H
L
H
L
X
Address
Command
Burst Stop
READ/WRITE
Active
PRE/PREA
Refresh
MRS
Burst Stop
READ/WRITE
Active
PRE/PREA
Refresh
MRS
Burst Stop
READ
WRITE
Active
PRE/PREA
Refresh
MRS
ILLEGAL*2
ILLEGAL*2
ILLEGAL*2
Action
BA, CA, A
10
BA, RA
BA, A
10
X
Op-Code, Mode-Add
X
BA, CA, A
10
BA, RA
BA, A
10
X
Op-Code, Mode-Add
X
BA, CA, A
10
BA, CA, A
10
BA, RA
BA, A
10
X
Op-Code, Mode-Add
NOP*4(Idle after
t
RP
)
ILLEGAL
ILLEGAL
ILLEGAL*2
ILLEGAL*2
ILLEGAL*2
ILLEGAL*2
ILLEGAL
ILLEGAL
ILLEGAL*2
ILLEGAL*2
WRITE
ILLEGAL*2
ILLEGAL*2
ILLEGAL
ILLEGAL
ROW
ACTIVATING
(FROM ROW
ACTIVE TO
tRCD)
L
L
L
L
L
L
WRITE
RECOVERING
(DURING tWR
OR tCDLR)
L
L
L
L
L
L
L
Table 9-3. Functional truth table
- 36 -
REV. 1.0 November. 2. 2000