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K4H1G0838M-TCA0 Datasheet

  • K4H1G0838M-TCA0

  • 128Mb DDR SDRAM

  • 53頁

  • SAMSUNG   SAMSUNG

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128Mb DDR SDRAM
List of figures
Figure 1 : 128Mb Package Pinout
Figure 2 : Package dimension
Figure 3 :State digram
Figure 4 : Power up and initialization sequence
Figure 5 : Mode register set
Figure 6 : Mode register set sequence
Figure 7 : Extend mode register set
Figure 8 : Bank activation command cycle timing
Figure 9 : Burst read operation timing
Figure 10 : Burst write operation timing
Figure 11 : Read interrupted by a read timing
Figure 12 : Read interrupted by a write and burst stop timing
Figure 13 : Read interrupted by a precharge timing
Figure 14 : Write interrupted by a write timing
Figure 15 : Write interrupted by a read and DM timing
Figure 16 : Write interrupted by a precharge and DM timing
Figure 17 : Burst stop timing
Figure 18 : DM masking timing
Figure 19 : Read with auto precharge timing
Figure 20 : Write with auto precharge timing
Figure 21 : Auto refresh timing
Figure 22 : Self refresh timing
Figure 23 : Power down entry and exit timing
Figure 24 : Output Load Circuit (SSTL_2)
Figure 25 : I / V characteristics for input/output buffers:
pull-up(above) and pull-down(below)
Figure 26 : QFC timing on read operation
Figure 27 : QFC timing on write operation with tDQSSmax
Figure 28 : QFC timing on write operation with tDQSSmin
Figure 29 : QFC timing example for interrupted writes operation
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REV. 1.0 November. 2. 2000

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