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K4H1G0838M-TCA0 Datasheet

  • K4H1G0838M-TCA0

  • 128Mb DDR SDRAM

  • 669.26KB

  • 53頁(yè)

  • SAMSUNG   SAMSUNG

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128Mb DDR SDRAM
4. Command Truth Table
COMMAND
Register
Register
Extended MRS
Mode Register Set
Auto Refresh
Refresh
Entry
Self
Refresh
Exit
CKEn-1
CKEn
CS
RAS
CAS
WE
BA
0,1
A
10
/AP
A
11,
A
9
~ A
0
Note
H
H
H
X
X
H
L
H
X
X
L
L
L
L
H
L
L
L
L
L
H
X
L
H
L
L
L
H
X
H
L
L
L
H
H
X
H
H
V
V
OP CODE
OP CODE
X
1, 2
1, 2
3
3
3
3
L
H
H
X
Row Address
L
H
L
H
X
V
X
L
H
X
Column
Address
(A
0
~A
9
)
Column
Address
(A
0
~A
9
)
Bank Active & Row Addr.
Read &
Column Address
Write &
Column Address
Burst Stop
Precharge
Bank Selection
All Banks
Entry
Exit
Entry
Precharge Power Down Mode
Exit
DM
No operation (NOP) : Not defined
Auto Precharge Disable
Auto Precharge Enable
Auto Precharge Disable
Auto Precharge Enable
4
4
4
4, 6
7
H
H
H
X
X
X
L
L
L
H
L
X
H
L
H
L
H
H
L
X
V
X
X
H
X
V
X
L
H
H
X
V
X
X
H
X
V
L
L
L
X
V
X
X
H
X
V
V
5
Active Power Down
H
L
H
L
H
L
X
X
L
H
H
H
X
X
H
X
H
X
8
9
9
X
H
L
X
H
Table 8. Command truth table
(V=Valid, X=Don鈥瞭 Care, H=Logic High, L=Logic Low)
1. OP Code : Operand Code. A
0
~ A
11
& BA
0
~ BA
1
: Program keys. (@EMRS/MRS)
2.EMRS/ MRS can be issued only at all banks precharge state.
A new command can be issued 2 clock cycles after EMRS or MRS.
3. Auto refresh functions are same as the CBR refresh of DRAM.
The automatical precharge without row precharge command is meant by "Auto".
Auto/self refresh can be issued only at all banks precharge state.
4. BA
0
~ BA
1
: Bank select addresses.
If both BA
0
and BA
1
are "Low" at read, write, row active and precharge, bank A is selected.
If both BA
0
is "High" and BA
1
is "Low" at read, write, row active and precharge, bank B is selected.
If both BA
0
is "Low" and BA
1
is "High" at read, write, row active and precharge, bank C is selected.
If both BA
0
and BA
1
are "High" at read, write, row active and precharge, bank D is selected.
5. If A
10
/AP is "High" at row precharge, BA
0
and BA
1
are ignored and all banks are selected.
6. During burst write with auto precharge, new read/write command can not be issued.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at t
RP
after the end of burst.
7. Burst stop command is valid at every burst length.
8. DM sampled at the rising and falling edges of the DQS and Data-in are masked at the both edges (Write DM latency is 0).
9. This combination is not defined for any function, which means "No Operation(NOP)" in DDR SDRAM.
- 33 -
REV. 1.0 November. 2. 2000

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