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K4H1G0838M-TCA0 Datasheet

  • K4H1G0838M-TCA0

  • 128Mb DDR SDRAM

  • 53頁

  • SAMSUNG   SAMSUNG

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128Mb DDR SDRAM
Burst Address Ordering for Burst Length
Burst
Length
2
Starting
Address(A2, A1, A0)
xx0
xx1
x00
4
x01
x10
x11
000
001
010
8
011
100
101
110
111
Sequential Mode
0, 1
1, 0
0, 1, 2, 3
1, 2, 3, 0
2, 3, 0, 1
3, 0, 1, 2
0, 1, 2, 3, 4, 5, 6, 7
1, 2, 3, 4, 5, 6, 7, 0
2, 3, 4, 5, 6, 7, 0, 1
3, 4, 5, 6, 7, 0, 1, 2
4, 5, 6, 7, 0, 1, 2, 3
5, 6, 7, 0, 1, 2, 3, 4
6, 7, 0, 1, 2, 3, 4, 5
7, 0, 1, 2, 3, 4, 5, 6
Interleave Mode
0, 1
1, 0
0, 1, 2, 3
1, 0, 3, 2
2, 3, 0, 1
3, 2, 1, 0
0, 1, 2, 3, 4, 5, 6, 7
1, 0, 3, 2, 5, 4, 7, 6
2, 3, 0, 1, 6, 7, 4, 5
3, 2, 1, 0, 7, 6, 5, 4
4, 5, 6, 7, 0, 1, 2, 3
5, 4, 7, 6, 1, 0, 3, 2
6, 7, 4, 5, 2, 3, 0, 1
7, 6, 5, 4, 3, 2, 1, 0
Table 4. Burst address ordering for burst length
DLL Enable/Disable
The DLL must be enabled for normal operation. DLL enable is required during power-up initialization, and
upon returing to normal operation after having disabled the DLL for the purpose of debug or evaluation (upon
exiting Self Refresh Mode, the DLL is enabled automatically). Any time the DLL is enabled, 200 clock cycles
must occur before a READ command can be issued.
Output Drive Strength
The normal drive strength for all outputs is specified to be SSTL_2, Class II. Some vendors might also support
a weak driver strength option, intended for lighter load and/or point-to-point environments. I-V curves for the
normal drive strength and weak drive strength will be included in a future revision of this document.
Mode Register Set
0
CK
CK
Command
t
CK
Precharge
All Banks
*1
Mode
Register Set
Any
Command
1
2
3
4
5
6
7
8
t
RP
*2
2 Clock min.
*1 : MRS can be issued only at all bank precharge state.
*2 : Minimum
t
RP
is required to issue MRS command.
Figure 6. Mode Register Set sequence
- 16 -
REV. 1.0 November. 2. 2000

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