128Mb DDR SDRAM
9. AC Operating Test Conditions
(V
DD
=2.5V, V
DDQ
=2.5V, T
A
= 0 to 70擄C)
Parameter
Input reference voltage for Clock
Input signal maximum peak swing
Input signal minimum slew rate
Input Levels(V
IH
/V
IL
)
Input timing measurement reference level
Output timing measurement reference level
Output load condition
Value
0.5 * V
DDQ
1.5
1.0
V
REF
+0.31/V
REF
-0.31
V
REF
V
tt
See Load Circuit
Unit
V
V
V/ns
V
V
V
Note
Table 15. AC operating test conditions
V
tt
=0.5*V
DDQ
R
T
=50鈩?/div>
Output
Z0=50鈩?/div>
C
LOAD
=30pF
V
REF
=0.5*V
DDQ
Figure 24. Output Load Circuit (SSTL_2)
10. Input/Output Capacitance
(V
DD
=2.5, V
DDQ
=2.5V, T
A
= 25
擄C
, f=1MHz)
Parameter
Input capacitance
(A
0
~ A
11
, BA
0
~ BA
1,
CKE, CS, RAS,CAS, WE)
Input capacitance( CK, CK )
Data & DQS input/output capacitance
Input capacitance(DM)
Symbol
C
IN1
C
IN2
C
OUT
C
IN3
Min
2
2
4.0
4.0
Max
3.0
3.0
5.0
5.0
Delta Cap(max)
0.5
0.25
0.5
Unit
pF
pF
pF
pF
Table 16. Input/output capacitance
- 46 -
REV. 1.0 November. 2. 2000
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