最新免费av在线观看,亚洲综合一区成人在线,中文字幕精品无码一区二区三区,中文人妻av高清一区二区,中文字幕乱偷无码av先锋

K4H1G0438M-TCA0 Datasheet

  • K4H1G0438M-TCA0

  • 128Mb DDR SDRAM

  • 669.26KB

  • 53頁(yè)

  • SAMSUNG   SAMSUNG

掃碼查看芯片數(shù)據(jù)手冊(cè)

上傳產(chǎn)品規(guī)格書(shū)

PDF預(yù)覽

128Mb DDR SDRAM
3.3.8 Write Interrupted by a Precharge & DM
A burst write operation can be interrupted before completion of the burst by a precharge of the same bank.
Random column access is allowed. A write recovery time(tWR) is required from the last data to precharge
command. When precharge command is asserted, any residual data from the burst write cycle must be
masked by DM.
< Burst Length=8 >
CK
CK
Command
DQS
t
WPRES*5
t
WR
Dina
0
Dina
1
Dina
2
Dina
3
Dina
4
Dina
5
Dina
6
Dina
7
Dinb
0
0
1
2
3
4
5
6
7
8
NOP
WRITE A
NOP
NOP
NOP
NOP
Precharge
WRITEB
NOP
t
DQSSmax
DQ
鈥瞫
t
DQSSmin
DQS
DQ
鈥瞫
DM
t
WPRES*5
Dina
0
Dina
1
Dina
2
Dina
3
Dina
4
Dina
5
Dina
6
Dina
7
Dinb
0
Dinb
1
Figure 16. Write interrupted by a precharge and DM timing
Precharge timing for Write operations in DRAMs requires enough time to allow 鈥渨rite recovery鈥?which is the
time required by a DRAM core to properly store a full 鈥?鈥?or 鈥?鈥?level before a Precharge operation. For DDR
SDRAM, a timing parameter, tWR, is used to indicate the required amount of time between the last valid write
operation and a Precharge command to the same bank.
The precharge timing for writes is a complex definition since the write data is sampled by the data strobe and
the address is sampled by the input clock. Inside the SDRAM, the data path is eventually synchronized with
the address path by switching clock domains from the data strobe clock domain to the input clock domain.
This makes the definition of when a precharge operation can be initiated after a write very complex since the
write recovery parameter must reference only the clock domain that is used to time the internal write operation,
i.e., the input clock domain.
tWR starts on the rising clock edge after the last possible DQS edge that strobed in the last valid data and
ends on the rising clock edge that strobes in the precharge command.
1. For the earliest possible Precharge command following a Write burst without interrupting the burst, the
minimum time for write recovery is defined by tWR.
2. When a precharge command interrupts a Write burst operation, the data mask pin, DM, is used to mask
input data during the time between the last valid write data and the rising clock edge on which the
Precharge command is given. During this time, the DQS input is still required to strobe in the state of DM.
The minimum time for write recovery is defined by tWR.
- 26 -
REV. 1.0 November. 2. 2000

K4H1G0438M-TCA0相關(guān)型號(hào)PDF文件下載

您可能感興趣的PDF文件資料

熱門(mén)IC型號(hào)推薦

掃碼下載APP，
一鍵連接廣大的電子世界。

在線(xiàn)人工客服

買(mǎi)家服務(wù)：
賣(mài)家服務(wù)：
技術(shù)客服：

0571-85317607

網(wǎng)站技術(shù)支持

13606545031

客服在線(xiàn)時(shí)間周一至周五
9:00-17:30

關(guān)注官方微信號(hào)，
第一時(shí)間獲取資訊。

建議反饋
返回頂部

建議反饋

聯(lián)系人：

聯(lián)系方式：

按住滑塊，拖拽到最右邊
>>
感謝您向阿庫(kù)提出的寶貴意見(jiàn)，您的參與是維庫(kù)提升服務(wù)的動(dòng)力！意見(jiàn)一經(jīng)采納，將有感恩紅包奉上哦！