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K4H1G0438M-TCA0 Datasheet

  • K4H1G0438M-TCA0

  • 128Mb DDR SDRAM

  • 669.26KB

  • 53頁

  • SAMSUNG   SAMSUNG

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128Mb DDR SDRAM
3.3.6 Write Interrupted by a Write
A Burst Write can be interrupted before completion of the burst by a new Write command, with the only restric-
tion that the interval that separates the commands must be at least one clock cycle. When the previous burst
is interrupted, the remaining addresses are overridden by the new address and data will be written into the
device until the programmed burst length is satisfied.
< Burst Length=4 >
CK
CK
Command
DQS
DQ
鈥瞫
Din A
0
Din A
1
Din B
0
Din B
1
Din B
2
Din B
3
0
1
1t
CK
2
3
4
5
6
7
8
NOP
WRITE A
WRITE b
NOP
NOP
NOP
NOP
NOP
NOP
Figure 14. Write interrupted by a write timing
- 24 -
REV. 1.0 November. 2. 2000

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