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K4H510438M-TCA0 Datasheet

  • K4H510438M-TCA0

  • 128Mb DDR SDRAM

  • 53頁(yè)

  • SAMSUNG   SAMSUNG

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128Mb DDR SDRAM
12. QFC function
QFC definition
when drive low on reads coincident with the start of DQS, this DRAM output signal says that one cycle later
there will be the first valid DQS output and returned to HI-Z after this finishing a burst operation. It is also
driven low shortly after a write command is received and returned to HI-Z shortly after the last data strobe
transition is received. Whenever the device is in standby, the signal is HI-Z. DQS is intended to enable an
external data switch. QFC can be enabled or disabled through EMRS control.
QFC timing on Read operation
QFC on reads is enabled coincident with the start of DQS preamble, and disabled coincident with the end of
DQS postamble
CL = 2, BL = 2
0
CK
CK
Command
DQS
DQ鈥?/div>
S
QFC
1
2
3
4
5
6
7
8
Read
Dout 0 Dout 1
Hi-Z
t
QCS
t
QCH
Figure 26. QFC timing on read operation
- 51 -
REV. 1.0 November. 2. 2000

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