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K4H510438M-TCA0 Datasheet

  • K4H510438M-TCA0

  • 128Mb DDR SDRAM

  • 53頁

  • SAMSUNG   SAMSUNG

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128Mb DDR SDRAM
3.3.7 Write Interrupted by a Read & DM
A burst write can be interrupted by a read command of any bank. The DQ鈥檚 must be in the high impedance
state at least one clock cycle before the interrupting read data appear on the outputs to avoid data contention.
When the read command is registered, any residual data from the burst write cycle must be masked by DM.
The delay from the last data to read command (tCDLR) is required to avoid the data contention DRAM inside.
Data that are presented on the DQ pins before the read command is initiated will actually be written to the
memory. Read command interrupting write can not be issued at the next clock edge of that of write command.
< Burst Length=8, CAS Latency=2 >
0
CK
CK
Command
DQS
CAS Latency=2
DQ
鈥瞫
t
DQSSmin
NOP
WRITE
NOP
NOP
NOP
READ
NOP
NOP
NOP
1
2
3
4
5
6
7
8
t
DQSSmax
t
WPRES*5
Din 0
Din 1
Din 2
Din 3
t
CDLR
Din 4
Din 5
Din 6
Din 7
Dout 0 Dout 1 Dout 2 Do
t
CDLR
DQS
CAS Latency=2
DQ
鈥瞫
DM
t
WPRES*5
Din 0
Din 1
Din 2
Din 3
Din 4
Din 5
Din 6
Din 7
Dout 0 Dout 1 Dout 2 Do
Figure 15. Write interrupted by a read and DM timing
The following function established how a Read command may interrupt a Write burst and which input data is
not written into the memory.
1. For Read commands interrupting a Write burst, the minimum Write to Read command delay is 2 clock
cycles. The case where the Write to Read delay is 1 clock cycle is disallowed
2. For Read commands interrupting a Write burst, the DM pin must be used to mask the input data words
whcich immediately precede the interrupting Read operation and the input data word which immediately
follows the interrupting Read operation
3. For all cases of a Read interrupting a Write, the DQ and DQS buses must be released by the driving chip
(i.e., the memory controller) in time to allow the buses to turn around before the DDR SDRAM drives them
during a read operation.
4. If input Write data is masked by the Read command, the DQS input is ignored by the DDR SDRAM.
5. Refer to "3.3.2 Burst write operation"
- 25 -
REV. 1.0 November. 2. 2000

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