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K4H280438M-TCA0 Datasheet

  • K4H280438M-TCA0

  • 128Mb DDR SDRAM

  • 53頁

  • SAMSUNG   SAMSUNG

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128Mb DDR SDRAM
1. Key Features
1.1 Features
鈥?/div>
Double-data-rate architecture; two data transfers per clock cycle
鈥?Bidirectional data strobe(DQS)
鈥?Four banks operation
鈥?Differential clock inputs(CK and CK)
鈥?DLL aligns DQ and DQS transition with CK transition
鈥?MRS cycle with address key programs
-. Read latency 2, 2.5 (clock)
-. Burst length (2, 4, 8)
-. Burst type (sequential & interleave)
鈥?All inputs except data & DM are sampled at the positive going edge of the system clock(CK)
鈥?Data I/O transactions on both edges of data strobe
鈥?Edge aligned data output, center aligned data input
鈥?LDM,UDM/DM for write masking only
鈥?Auto & Self refresh
鈥?15.6us refresh interval(4K/64ms refresh)
鈥?Maximum burst refresh cycle : 8
鈥?66pin TSOP II package
1.2 Operating Frequencies
- A2(DDR266A)
Speed @CL2
Speed @CL2.5
DLL jitter
133MHz@CL2
-
鹵0.75ns
- B0(DDR266B)
100MHz
133MHz
鹵0.75ns
- A0(DDR200)
100MHz
-
鹵0.8ns
*CL : Cas Latency
Table 1. Operating frequency and DLL jitter
- 9 -
REV. 1.0 November. 2. 2000

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