128Mb DDR SDRAM
Parameter
Exit self refresh to bank active command
Exit self refresh to read command
Refresh interval time
64Mb, 128Mb
256Mb
Output DQS valid window
Clock half period
DQS write postamble time
QFC setup to first DQS edge on reads
QFC hold after last DQS edge on reads
Write command to QFC delay on write
Write burst end to QFC delay on write
Write burst end to QFC delay on write
interrupted by Precharge
Symbol
tXSA
tXSR
tREF
tQH
tHP
tWPST
tQCS
tQCH
tQCSW
tQCHW
tQCHWI
1.25ns
-
-A2(PC266@CL=2) -B0(PC266@CL=2.5) -A0(PC200@CL=2)
Min
75
200
15.6
7.8
tHPmin
-0.75ns
tCLmin
or tCHmin
0.25
0.9
0.4
-
-
Max
Min
75
200
15.6
7.8
tHPmin
-0.75ns
tCLmin
or tCHmin
0.25
-
-
Max
Min
80
200
15.6
7.8
tHPmin
-1.0ns
tCLmin
or tCHmin
0.25
-
-
Max
ns
Cycle
us
us
ns
ns
tCK
4
1
1
7
Unit
Note
1.1
0.6
4.0
0.5tCK
1.5tCK
0.9
0.4
1.1
0.6
4.0
0.9
0.4
1.1
0.6
4.0
tCK
tCK
ns
5
6
1.25ns
-
0.5tCK
1.5tCK
1.25ns
-
0.5tCK
1.5tCK
1. Maximum burst refresh of 8
2. tHZQ transitions occurs in the same access time windows as valid data transitions. These parameters are not referenced
to a specific voltage level, but specify when the device output is no longer driving.
3. The specific requirement is that DQS be valid(High or Low) on or before this CK edge. The case shown(DQS going from
High_Z to logic Low) applies when no writes were previously in progress on the bus. If a previous write was in progress,
DQS could be High at this time, depending on tDQSS.
4. The maximum limit for this parameter is not a device limit. The device will operate with a great value for this parameter,
but system performance (bus turnaround) will degrade accordingly.
5. The value of tQCSW min. is 1.25ns from the last low going data strobe edge to QFC high. And the value of
tQCSW max. is 0.5tcK from the first high going clock edge after the last low going data strobe edge to QFC
high.
6. the value of tQCSWI max. is 1.5tcK from the first high going clock edge after the last low going data strobe
edge to QFC high.
7. A write command can be applied with tRCD satisfied after this command.
Table 14. AC timing parameters and specifications
- 45 -
REV. 1.0 November. 2. 2000