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K4D263238M-QC60 Datasheet

  • K4D263238M-QC60

  • 1M x 32Bit x 4 Banks Double Data Rate Synchronous RAM with B...

  • 19頁

  • SAMSUNG   SAMSUNG

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K4D263238M
FUNCTIONAL DESCRIPTION
鈥?/div>
Power-Up Sequence
128M DDR SDRAM
DDR SDRAMs must be powered up and initialized in a predefined manner to prevent undefined operations.
1. Apply power and keep CKE at low state (All other inputs may be undefined)
- Apply VDD before VDDQ .
- Apply VDDQ before VREF & VTT
2. Start clock and maintain stable condition for minimum 200us.
3. The minimum of 200us after stable power and clock(CK,CK ), apply NOP and take CKE to be high.
4. Issue precharge command for all banks of the device.
5. Issue a EMRS command to enable DLL
*1
6. Issue a MRS command to reset DLL. The additional 200 clock cycles are required to lock the DLL.
*
1,2
7. Issue precharge command for all banks of the device.
8. Issue at least 2 or more auto-refresh commands.
9. Issue a mode register set command with A8 to low to initialize the mode register.
*1 The additional 200cycles of clock input is required to lock the DLL after enabling DLL.
*2 Sequence of 6&7 is regardless of the order.
Power up & Initialization Sequence
0
CK
CK
t
RP
2 Clock min.
2 Clock min.
precharge
ALL Banks
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
鈭?/div>
鈭?鈭?/div>
鈭?/div>
Command
precharge
ALL Banks
EMRS
MRS
DLL Reset
鈭?/div>
1st Auto
Refresh
2nd Auto
Refresh
鈭?鈭?/div>
鈭?鈭?/div>
tRP
t
RFC
鈭?/div>
鈭?/div>
t
RFC
2 Clock min.
Mode
Register Set
Any
Command
Inputs must be
stable for 200us
鈭?/div>
鈭?/div>
200 Clock min.
- 8 -
Rev. 1.3 (Aug. 2001)

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