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K4D263238M-QC60 Datasheet

  • K4D263238M-QC60

  • 1M x 32Bit x 4 Banks Double Data Rate Synchronous RAM with B...

  • 19頁

  • SAMSUNG   SAMSUNG

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K4D263238M
1M x 32Bit x 4 Banks Double Data Rate Synchronous RAM
with Bi-directional Data Strobe and DLL
FEATURES
鈥?2.5V 鹵 5% power supply
鈥?SSTL_2 compatible inputs/outputs
鈥?4 banks operation
鈥?MRS cycle with address key programs
-. Read latency 3,4 (clock)
-. Burst length (2, 4, 8 and Full page)
-. Burst type (sequential & interleave)
鈥?Full page burst length for sequential burst type only
鈥?Start address of the full page burst should be even
鈥?All inputs except data & DM are sampled at the positive
going edge of the system clock
鈥?Differential clock input
鈥?No Write Interrupted by Read function
128M DDR SDRAM
鈥?Data I/O transactions on both edges of Data strobe
鈥?DLL aligns DQ and DQS transitions with Clock transition
鈥?Edge aligned data & data strobe output
鈥?Center aligned data & data strobe input
鈥?DM for write masking only
鈥?Auto & Self refresh
鈥?32ms refresh period (4K cycle)
鈥?100pin TQFP package
鈥?Maximum clock frequency up to 222MHz
鈥?Maximum data rate up to 444Mbps/pin
ORDERING INFORMATION
Part NO.
K4D263238M-QC45
K4D263238M-QC50
K4D263238M-QC55
K4D263238M-QC60
Max Freq.
222MHz
200MHz
183MHz
166MHz
Max Data Rate
444Mbps/pin
400Mbps/pin
366Mbps/pin
333Mbps/pin
SSTL_2
100 TQFP
Interface
Package
GENERAL DESCRIPTION
FOR 1M x 32Bit x 4 Bank DDR SDRAM
The K4D263238 is 134,217,728 bits of hyper synchronous data rate Dynamic RAM organized as 4 x 1,048,576 words by
32 bits, fabricated with SAMSUNG
鈥?/div>
s high performance CMOS technology. Synchronous features with Data Strobe allow
extremely high performance up to
1.8GB/s/chip.
I/O transactions are possible on both edges of the clock cycle. Range of
operating frequencies, programmable burst length and programmable latencies allow the device to be useful for a variety
of high performance memory system applications.
- 4 -
Rev. 1.3 (Aug. 2001)

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