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K4H560438E-GLB3 Datasheet

  • K4H560438E-GLB3

  • 256Mb E-die DDR SDRAM Specification 60Ball FBGA (x4/x8)

  • 244.76KB

  • 24頁

  • SAMSUNG   SAMSUNG

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DDR SDRAM 256Mb E-die (x4, x8)
Key Features
鈥?Double-data-rate architecture; two data transfers per clock cycle
鈥?Bidirectional data strobe
[DQ] (x4,x8)
Four banks operation
鈥?Differential clock inputs(CK and CK)
鈥?DLL aligns DQ and DQS transition with CK transition
鈥?MRS cycle with address key programs
-. Read latency 2, 2.5 (clock)
-. Burst length (2, 4, 8)
-. Burst type (sequential & interleave)
鈥?All inputs except data & DM are sampled at the positive going edge of the system clock(CK)
鈥?Data I/O transactions on both edges of data strobe
鈥?Edge aligned data output, center aligned data input
鈥?DM for write masking only (x4, x8)
鈥?Auto & Self refresh
鈥?7.8us refresh interval(8K/64ms refresh)
鈥?Maximum burst refresh cycle : 8
鈥?60Ball FBGA package
DDR SDRAM
Ordering Information
Part No.
K4H560438E-GC/LB3
K4H560438E-GC/LA2
K4H560438E-GC/LB0
K4H560838E-GC/LB3
K4H560838E-GC/LA2
K4H560838E-GC/LB0
32M x 8
64M x 4
Org.
Max Freq.
B3(DDR333@CL=2.5)
A2(DDR266@CL=2)
B0(DDR266@CL=2.5)
B3(DDR333@CL=2.5)
A2(DDR266@CL=2)
B0(DDR266@CL=2.5)
SSTL2
60 FBGA
SSTL2
60 FBGA
Interface
Package
Operating Frequencies
B3(DDR333@CL=2.5)
CL-tRCD-tRP
Speed @CL2
Speed @CL2.5
2.5-3-3
133MHz
166MHz
A2(DDR266@CL=2)
2-3-3
133MHz
133MHz
B0(DDR266@CL=2.5)
2.5-3-3
100MHz
133MHz
*CL : CAS Latency
Rev. 1.3 April, 2005

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